As reported, the "fab club" — IBM, Chartered, Infineon and Samsung — have produced chips on a common 45-nm process technology. The four companies announced Tuesday (Aug. 29) that they have developed their first functional chips based on a low-power, 45-nm process technology.

The jointly-developed, 45-nm process is a "design-specific" technology, supporting copper interconnects, low-k dielectrics, strained silicon and other features, said Subramanian Iyer, a distinguished engineer from IBM Corp. and director of the company's 45-nm and eTechnologies Collaboration Solutions unit.

The critical layers of the 10-metal-level technology are expected to be processed using scanners based on 193-nm immersion lithography with a numerical aperture of 1.2, Iyer said. Previously, the chip makers in the loose alliance have been using "dry" 193-nm lithography scanners for 65-nm production.

Iyer declined to comment on the lithography vendor being used for the 45-nm technology. Sources believe that IBM, Chartered, Infineon and Samsung are reportedly expected to deploy 193-nm immersion scanners from ASML Holding NV of the Netherlands.

"I can't comment on that," he said in an interview. "But at this point, we're thrilled with the results [with immersion lithography]."

The 45-nm process also supports a low-k film with a dielectric constant of 2.4, Iyer said. For 65-nm production, the low-k film has a dielectric constant of 2.7.

Both films are carbon-doped-oxide technologies based on IBM's own recipe, dubbed SiCOH. IBM's proprietary film is devised by using chemical vapor deposition (CVD) tools.

Not surprisingly, the "fab club" decided not to use high-k dielectrics for gate-stack applications at 45-nm. Instead, the companies will deploy workhorse silicon dioxide technology for the gate, he said. "For 45-nm, we don't think we need to use high-k," he said.

In most cases, high-k is simply not ready for gate-stack applications at 45-nm and will be most likely pushed out to the 32-nm node, according to industry analysts.

The IBM-led, collaborative effort will deploy strained silicon for the 45-nm node, but not silicon-on-insulator (SOI) technology. "Advanced strain engineering techniques are the cornerstone for performance," according to a spokesman for IBM. "SOI is a separate effort and is available through IBM, but is not part of the IBM-Chartered-Infineon-Samsung common platform."