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San Jose, Calif. — The arcane realm
of electrostatic discharge will finally
reach the limelight--and perhaps the
boiling point--this month as a group of
leading
chip makers pushes to reduce the
specifications for ESD in digital ICs.
But some detractors suggest that
lowering ESD levels is reckless, and
could lead to catastrophic quality and
reliability problems for semiconductors.
The Industry Council on ESD Target
Levels is expected to hammer out a white
paper at the International Electrostatic
Discharge Workshop, which convenes May
14-17 in Lake Tahoe, Calif., in support
of a proposal to reduce on-chip ESD
stress target levels by more than half.
The reduction is supposed to lower cycle
times and costs for chip makers, which
are struggling to meet the current ESD
levels in new designs. According to the
council, those levels are outdated and
represent "overkill," causing
unnecessary debugging time, IC respins
and product delays. The group maintains
that its proposal will not compromise
quality or performance.
The council, which hopes to muster
industry consensus around its plan by
2008, will present its white paper to
the Jedec standards body. Jedec is not
expected to recognize the proposal as a
formal standard, but may endorse or
"classify" the new ESD target levels.
As both chips and systems become
smaller and more complex, product
failures increase in tandem with the
levels of electrostatic discharge. The
cost for ESD-damaged devices ranges from
a few cents for a simple
diode to several hundred dollars for
complex hybrids, according to the
Electrostatic Discharge Association, a
group based in Rome, N.Y.
Besides devising new target levels,
the Industry Council on ESD Target
Levels is also attempting to gain
acceptance
for the proposed ESD levels among
their respective customers. The council,
which was formed last year, consists of
16 major companies:
Analog Devices, Advanced Micro De-
vices, Freescale, Fujitsu, IBM, Infineon,
Intel, LSI, Matsushita, NXP, Oki,
Renesas, Samsung, Sarnoff, Texas
Instruments and TSMC.
But given the fact that OEMs are
under pressure to boost the ESD
protection levels in their products,
system makers are reportedly unhappy
with the efforts to lower the standards.
Lowering the ESD levels "is kind of a
joke," said one vendor. "What you're
doing is giving up reliability. In other
words, the semiconductor community is
passing the buck and making ESD someone
else's problem."
Even one ESD council member contends
that reduced ESD levels spell potential
trouble for the electronics industry. "I
don't think it's a good idea," said Koen
Verhaege, executive director of Sarnoff
Europe, part of Sarnoff Corp.
(Princeton, N.J.). "Changing the
standard specifications today, without
proper data and without decisive and
objective proof that indeed quality and
yield will not suffer, is reckless and
could be lethal to divisions, to
companies and to businesses."
Sarnoff is a supplier of intellectual
property for ESD protection, and some
contend that the company's opposition
may be tied to its
IP business, which could be
threatened if the ESD target levels are
lowered. "They do not make ICs, so their
motives may be different than ours,"
said Charvaka Duvvury, a fellow in Texas
Instruments Inc.'s Silicon Technology
Group and one of the industry's foremost
experts on ESD.
Duvvury claimed that current ESD
target levels are "overkill" for today's
IC designs. He insisted that the lower
on-chip ESD target levels the council is
proposing will not affect chip quality,
reliability or performance. In extensive
field tests conducted by the ESD
council, digital chips with reduced ESD
levels had relatively few problems or
field returns, he said.
The only challenge now is convincing
the customers. "Naturally, there will be
a pushback," Duvvury said. "One of the
concerns among customers is that we're
doing this for our own benefit."
But "it would not be in the chip
makers' best interests to lower the ESD
levels unless it was safe [to do so],"
said Will Strauss, president of market
research house Forward Concepts Co.
(Tempe, Ariz.). "I would side with the
people that make the chips."
George Dudnikov, senior vice
president and chief technology officer
for the pc-board and backplane divisions
at Sanmina-SCI Corp. (San Jose), said
it's far too early to tell if the
proposed ESD target levels will have an
overall impact on IC quality. But, he
warned, "if yields begin to suffer,
there might be a rebellion in the
industry."
Sanmina-SCI, one of the world's
largest contract electronics
manufacturers, is taking matters into
its own hands. Along with development
partner Shocking Technologies Inc., the
company is devising a board-level
embedded ESD solution. The technology
essentially shifts ESD protection from
the chip to the board, Dudnikov said.
For years, OEMs have implemented ESD
protection on three fronts: the system,
the board and within the chip itself. On
the system side, OEMs tend to use
standalone ESD devices, designed to
protect a sudden static surge within a
specific I/O, connector or other
component. ESD devices adhere to the IEC
6100-4-2 immunity requirements, which
call for a 15,000-volt air discharge
level and a 8,000-V direct-contact
specification.
"For systems houses, the quality of
the manufacturer is at stake. So, ESD is
becoming more and more important," said
Tom Dugan, director of marketing for
Semtech Corp. (Camar- illo, Calif.), a
supplier of ESD protection devices and
other products.
On the device side of the equation,
all chip designs must integrate
specialized diodes or other on-chip
discrete circuitry for ESD protection.
Many chip makers have their own,
internal ESD solutions, but Freescale,
Sarnoff and a few others sell or license
their respective technologies.
The Industry Council on ESD Target
Levels--an ad hoc group that is not
associated with the Electrostatic
Discharge Association--has already
proposed changes to two main
device-level stress-testing standards
for ESD: the Human Body Model and the
Machine Model.
For more than two decades, chip
makers have developed digital IC
products with on-chip ESD protection
circuitry that supports the 2,000-V
level for the Human Body Model (HBM) and
the 200-V level for the Machine Model
(MM). Under the new proposal, the ESD
council is pushing the industry to lower
the HBM level to 1,000 V and the MM
target to 30 V.
The HBM test simulates the electronic
transfer of a charge from a human to a
device. The MM test simulates the
transfer of a charge from a machine to a
device. There is no proposed change for
the third major ESD target level, dubbed
the Charged Device Model. The CDM, which
simulates a charge from one device to
another, remains at 500 V.
Technically, the CDM, HBM or MM
specifications are not recognized by the
standards bodies. For years, chip makers
and their customers have accepted these
ESD specifications as a standard on an
ad hoc basis.
But at the 90-nanometer node and
beyond, the current device-level ESD
targets are too high, said Harald
Gossner, senior principal for ESD design
at Infineon Technologies AG (Munich,
Germany) and chairman of the Industry
Council on ESD Target Levels. ESD
specifications must be lowered in order
to reduce unnecessary time spent
debugging, which is "delaying the
time-to-market for ICs," Gossner warned.
Today's stringent device-level ESD
targets were originally devised some two
decades ago, when factory floors lacked
suitable ESD protection, and thus are
outdated, Gossner said. And as digital
ICs migrate down to the submicron realm,
it's a struggle for chip makers to meet
those standards, he said.
Among the problems is a shift toward
scaling ultrathin gate oxides in chip
designs. According to a paper from TI
(Dallas), that trend "is causing a
serious concern for both thermal damage
as well as latent damage from the
transients of the ESD pulse even with
the presence of a clamp."
The problem is even more complex for
system-on-chip products, especially RF-enabled
Bluetooth devices with digital
capabilities. The industry has long
accepted lower ESD protection levels for
RF and compound semiconductors.
"Much lower ESD performances are
accepted in compound semiconductor
devices (i.e., 250-V HBM in many GaAs
ICs) because no one to date has come up
with technically or economically
feasible on-chip protection solutions,"
a paper from Sarnoff noted.
Sarnoff, however, insists that it has
an IP solution for ESD protection at 90
nm and below. The company has licensed
its so-called TakeCharge ESD solution to
Epson, Renesas, Toshiba and others in
Japan. In that country, ESD protection
is a "selling point," said Sarnoff's
Verhaege.
"The technical literature indicates
that common ESD solutions are no longer
technically and/or economically viable
once you're designing below 90 nm, but
solutions do exist," he said.
Freescale Semiconductor Inc. is
taking a different and somewhat contra-
dictory approach. On the one hand, Free-
scale licenses its proprietary ESD
protection technology to outside
companies. On the other hand, it is also
endorsing the lower ESD standards that
the industry council is proposing.
Jim Miller, design manager for ESD
products at Freescale, said the Austin,
Texas, company is attempting to gain a
consensus for lower ESD standards in the
industry as well as within Freescale
itself. "The idea is to get the Q&A
[quality assurance] folks on board," he
said. "We are trying to lobby the goals
within our own company."
On the systems front, Semtech last
week expanded its family of standalone
low-capacitance protection devices. Its
RailClamp line provides system designers
with ESD protection for high-speed
applications--without the high clamping
voltage and high capacitance of
competing solutions. The two devices,
RClamp 1502B and RClamp 2402B, are
designed with an ultralow capacitance of
0.6 picofarad to protect high-speed data
lines without signal attenuation,
Semtech's Dugan said.
Specialty polymers
In a novel approach, Sanmina-SCI is
using Shocking Technologies' specialty
polymers for embedding ESD protection
into printed-circuit boards. The
companies are developing voltage-switchable
dielectric materials--specialty polymers
that instantaneously change from
insulators to conductors when a
preprogrammed bidirectional voltage is
applied, said Lex Kosowsky, president
and CEO of Shocking Technologies Inc.
(San Jose).
"The technology is like an airbag in
a car," he said.
On another front, White Mountain Labs
(Phoenix), which provides ESD testing
services, last week formed a partnership
with SRF Technologies Inc. (Queen Creek,
Ariz.). SRF Technologies provides
companies in the semiconductor industry
with
I/O and ESD design support.
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