Below are some slides from recent Common Platform Technology Forum, the chip alliance of IBM, Globalfoundries and Samsung about the future direction of process integration. The Common Technology Platform and other vendors has been lagging Intel in process development and integration for several years. Their latest effort to catch up are:
"IBM sketched out its visions of the fab future at the recent Common Platform Technology Forum, the chip alliance of IBM, Globalfoundries and Samsung. IBM scientists spotlights that double patterning tricks with immersion lithography. Big Blue also showed advances in fully depleted silicon-on-insulator and plans for silicon photonics, nanowires"
" IBM, GloFo and Samsung now claim they have the lion's share of today's 32/28 nm, high-K metal gate capacity."
While they are claiming to have the fab capacity lead for 28nm HKMG process, Intel, TSMC, and other foundries would feel differently.
Chip makers must move to the “very
complex” process of double patterning with immersion lithography starting at 20
nm, Patton said. But IBM has worked on ways to hide much of that complexity
under either a standard cell design flow or for more advanced users a custom
flow based on a relatively simple algorithm he added.
After FinFETs, it's nanowires and photonics
The next big thing after FinFETS will be carbon nanotubes, said Patton. They offer a ten-fold performance boost but still contain too many metal impurities for commercial use, a problem IBM researchers are addressing.
“The next step is photonics, modulators controlling multiple nanophotonics waveguides with multiple frequencies--the trick is integrating them” in CMOS, he said, showing IBM's work above. “The ultimate is 3-D packaging and photonics,” he said showing a Holy Grail design (below) that could sport a TByte/second of bandwidth.
Mobile and cloud are the drivers
copyright 2013 Ron Maltiel all rights reserved