A summary of some of the key issues below in "Intel, rivals gird for IC manufacturing showdown" and in "IEDM preview: 20nm and belo" .
"There have been three primary drivers in the semiconductor industry for the last four decades: Area, power/performance and cost. The well-known push to cram more functionality onto a single chip through continued scaling -- or into a single package through 3D integration and other advanced packaging techniques -- has been well documented. Today, with the exception of Intel, the industry's leading edge devices in high volume manufacturing have critical dimensions of 28nm. Intel, racing ahead, introduced the 22nm IvyBridge chip in 2011 and has announced plans to have 14nm by the end of 2013. How long this kind of scaling can continue is the subject of some debate, with most recognizing the EUV lithography will be required at some point, most likely for the 10nm generation (Intel has said it doesn't need it for 14nm).
It's clear, though, that continued scaling is running out of steam..."
LONDON â€“ Chip giant Intel and the research partnership clustered around IBM and STMicroelectronics are each set to report progress on their approaches to leading-edge IC manufacturing during the International Electron Devices Meeting (IEDM) in San Francisco in December.
Research teams are set to present on the FinFET approach--called tri-gate by Intel--on fully-depleted silicon-on-insulator (FDSOI) and on bulk planar processes at around 20 nm and beyond.
Intel is set to deliver a paper on its 22-nm FinFET technology for SoC applications. In the same session, a research team drawn from CEA-Leti, STMicroelectronics, IBM, Globalfoundries and Renesas will present a paper on ultra-thin box and body (UTBB) FDSOI transistors for a multiple threshold voltage strategy at 20 nm and below.
ST will also report on switching energy efficiency in the UTTB process while IBM will describe a 22-nm SOI process. Meanwhile, Samsung researchers will deliver a research paper on the extensibility of its bulk 20-nm planar HKMG process.
Intel is already making processors using a 22-nm FinFET manufacturing process technology. It has described that process as a CPU process that was not optimized for lowest power consumption whereas the subject of the IEDM presentation is called an SoC process. Intel will provide engineering details of its 22-nm tri-gate SoC process and discuss its use of the approach to build a technology platform for SoC applications. That implies broad families of high-speed, low standby power and high voltage tolerant transistors, as well as RF and mixed-signal capabilities, according to the paper's abstract.
High-speed logic transistors have sub-threshold leakages ranging from 100-nA per micron to 1-nA per micron, while the low-power versions feature a leakage of less than 50-pA per micron. Nonetheless, the process retains 1.8- and 3.3-volt transistors for analog circuits, and legacy circuits.
The Intel 22-nm SoC platform also includes carbon-doped oxide interconnect and three different types of SRAM bit cell to provide options between density, performance and low voltage operation, according to the the abstract.
In another session on Dec. 11, a paper authored by a team from IBM, STMicroelectronics, Globalfoundries, Renesas, Soitec and CEA-Leti will report on another SOI process at 22-nm known as ETSOI for extremely thin silicon-on-insulator. This process has a silicon channel for n-type transistors and strained silicon-germanium channel for p-type transistors.
As the industry works to perfect 28nm devices in volume manufacturing and early 20nm processes, attention is focusing on next-generation 14nm and below technologies.
There have been three primary drivers in the semiconductor industry for the last four decades: Area, power/performance and cost. The well-known push to cram more functionality onto a single chip through continued scaling -- or into a single package through 3D integration and other advanced packaging techniques -- has been well documented. Today, with the exception of Intel, the industry's leading edge devices in high volume manufacturing have critical dimensions of 28nm. Intel, racing ahead, introduced the 22nm IvyBridge chip in 2011 and has announced plans to have 14nm by the end of 2013. How long this kind of scaling can continue is the subject of some debate, with most recognizing the EUV lithography will be required at some point, most likely for the 10nm generation (Intel has said it doesn't need it for 14nm).
It's clear, though, that continued scaling is running out of steam, and that the industry most look for other means by which to say on the path defined by the proverbial "Moore's Law." Those advances are one of the primary focal points of the upcoming 58th annual IEEE International Electron Devices Meeting (IEDM), which will take place December 10-12, 2012 at the San Francisco Hilton Union Square. The conference will be preceded by a day of short courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.
As reported in last month's issue, highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include Intel's unveiling of its industry-leading trigate manufacturing technology; a plethora of advances in memory technologies from numerous companies; IBM's demonstration of high-performance logic technology on flexible plastic substrates; continuing advances in the scaling of transistors to ever smaller sizes, and breakthroughs in many other areas that will continue to move electronics technology forward.
Following, we've assembled a list of the "be sure not to miss" papers and sessions slated for IEDM 2012.
In the plenary session, imec's Luc Van den hove, will describe how ultimate transistor and memory technologies are the core of a sustainable society. He says that several key societal challenges in domains such as healthcare, energy, urbanization and mobility call for sustainable solutions that can be enabled by combining various technologies. These solutions will be backboned by wireless sensor systems, smart mobile devices and huge data centers and servers, the key constituents of a new information universe. They will require extreme computation and storage capabilities, bound by (ultra)low-power or heat dissipation constraints, depending on the application. This drives the need, he says, to keep on scaling transistor technologies by tuning the three technology knobs: power/performance, area and cost. To get to ultra-small dimensions, advanced patterning integration, new materials such as high-mobility Ge and III-V materials, and new device architectures such as fully depleted devices are being introduced. This comes along with an increasing need for process complexity reduction and variability control. Equally important are the continued R&D efforts in scaling memory technologies. NAND Flash, DRAM and SRAM memories are now approaching the point where new scaling constraints force exploration of new materials, cell architectures and even new memory concepts. This opens opportunities for resistance based memories such as resistive RAM, phase-change RAM or spin-torque transfer magneto resistive RAM.
In another invited paper, in the regular sessions, researchers from Micron and Intel will discuss scaling directions for 2D and 3D NAND Cells. They note that many 2D NAND scaling challenges are addressed by a planar floating gate (FG) cell, which has a smaller aspect ratio and less cell to cell interference. Figure 1 compares a wrap FG cell (left) and a planar FG cell (right). The wrap cell is limited by a required aspect ratio of >10 for both the wordline and the bitline direction in a sub-20nm cell. The planar cell eliminates this limitation.
Of course, not all IEDM presentations are focused on leading-edge logic and memory. In the plenary session, John Rogers from the University of Illinois at Urbana-Champaign, will talk on bio-integrated electronics. He notes that biology is curved, soft and elastic, while silicon wafers are not. Semiconductor technologies that can bridge this gap in form and mechanics will create new opportunities in devices that require intimate integration with the human body. He plans to cover ideas for electronics, sensors and actuators that offer the performance of state-of-the-art, wafer-based systems but with the "mechanical properties of a rubber band." He'll explains the underlying materials science and mechanics of these approaches, and illustrate their use in bio-integrated, ‘tissue-like' devices with unique diagnostic and therapeutic capabilities, when conformally laminated onto the heart, brain or skin.
In the third plenary talk, Joo-Tae Moon of Samsung Display will give a talk titled "State of the Art and Future Prospects in Display Technologies." There are two parts which satisfy this vision, he notes. One is the picture quality and the other is design of the display. From picture quality point of view, bigger screen size and higher pixel density are the main factors. The need for a bigger screen size requires expediting technologies with lower RC delay and higher transistor performance. Higher pixel density mandates a smaller unit pixel area and each unit pixel has the dead space for the transistor and metal line which is protected from the light by the black matrix. Clearly, the design factor is the one of the main driving forces for the changes from CRT era to flat panel display era, he says.
imec, in a paper titled "Ultra Thin Hybrid Floating Gate and High-k Dielectric as IGD Enabler of Highly Scaled Planar NAND Flash Technology," will describe -- for the first time -- a demonstration of ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4 nm with improved performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacture and scalability for high density memory application. Figure 2 is a TEM image of a polysilicon/TiN HFG cell. The stack consists of an ISSG tunnel oxide, a dual layer FG (PVD polysilicon + PVD TiN), a high-k IPD (ALD Al2O3) and an n-type polysilicon CG.
Figure 2. A TEM image of a polysilicon/TiN HFG cell perpendicular to the CG direction. Source: imec.
In a paper jointly authored by GLOBALFOUNDRIES and Samsung, titled "Stress Simulations for Optimal Mobility Group IV p- and n-MOS FinFETs for the 14 nm Node and Beyond," researchers provide calculations of stress enhanced mobilities for n- and p-FinFETs with both Si and Ge channels for the 14 nm node and beyond. Results indicate that both for nFETs and pFETs, Ge is "very interesting," provided the correct stressors are used to boost mobility. Figure 3 is a XTEM of a Ge-channel FET with SiGe source/drain. They conclude that strained channels grown on a strain relaxed buffer is effective for 14nm nodes and scalable to future nodes. TCAD simulation trends are experimentally confirmed by nano-beam diffraction (NBD).
Ajit Manocha, CEO, GLOBALFOUNDRIES, Inc. is sure to provide an interesting luncheon talk on Tuesday, December 11th, addressing some recent jabs from Intel's Mark Bohr. The title of Manocha's talk: "Is the Fabless/Foundry Model Dead? We Don't Think So. Long Live Foundry 2.0!"
Manocha says that industry experts and observers have predicted for a long time that the fabless model has some cracks in it, and may in fact be headed for extinction at some point. "We in the foundry industry dismissed such chatter as we continue to enjoy growth rates that outpace the overall semiconductor industry," he notes in his pre-conference abstract. "But it wasn't until an executive from – surprise – Intel – officially declared the fabless model is collapsing recently that many of us really got our feathers ruffled. We firmly believe that the rumors of its death are greatly exaggerated. Evidence would seem to support that it is actually the IDM model which is dead, survived only by a very small number of anomalies that have either the financial wherewithal or stubbornness to continue down this path."
The foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together, says Manocha. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy. Recent talks of fabless companies investing in their own fabs, and of foundries developing ‘single company fabs' underscore the sense of urgency. "Clearly, we must change - Call it Foundry 2.0," he says.
Unprecedented technical and business challenges have driven semiconductor manufacturing to this new fork in the road. On the one side is the option to ‘go it alone', an option available to less than a handful of companies. The temptation here is to circle the wagons, dig deep into the bank and develop an optimized, but relatively closed, solution that will hopefully work for most every need. Manocha said a second option, ironically, is a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface' to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies. "With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration – early, often and deep – is really the only practical approach given the cost and complexities involved," he said.
One of the two evening panels on Tuesday at 8pm is titled "The Mighty Little Transistor: FinFETs to the Finish or Another Radical Shift?" The moderator will be Suresh Venkatesan of GLOBALFOUNDRIES. He notes that the 22nm node spelled the dawn of the fullly-depleted device architecture – with the implementation of FinFETs as the workhorse of the technology. However – projecting out to the 10nm node and beyond – the scalability of the FinFET architecture, the materials systems used to create it, and the fundamental electrostatics and parasitic components associated with the transistor once again loom large as significant challenges that need to be overcome.
copyright 2012 Ron Maltiel all rights reserved