1. Intel's 45-nm high-k metal-gate

Tom Cheyney, Chip Shots
Fabtech's Senior Contributing Editor                                                                           Dec 11, 2007 at 02:01 PM

 

No single International Electron Devices meeting (IEDM) paper was more eagerly anticipated---or cynically discounted---as Intel's morning presentation on the Big Kahuna's Moore's Law saving, production-worthy 45-nm logic technology featuring high-k dielectrics/metal gates. The conference room was full, but not to standing-room-only levels---and a fair portion of the crowd left soon after Kaizad Mistry spoke on behalf of the 50-person (!) coauthorship team. Many basic details of Intel's process technology have come out either through the company's own channels or other sources such as reverse process analysis outfits and the technologist rumor mill, so I won't try and review them all here. Here are some highlights, including what may be a few fresh tidbits (at least fresh to Chip Shots!): The hafnium-oxide high-k dielectric turns out to have an equivalent oxide thickness of 1.0 nm (about 18 to 20 angstroms). The process used is a high-k first, metal-gate-last approach, and those gates are deposited after high-temperature annealing.   Now into third-generation strained silicon, Mistry said the germanium portion of the SiGe cocktail had risen to 30% at 45 nm, and the SiGe has been moved closer to the channel.   Drive currents measured at the contact gate pitch are 12% better than 65 nm (best NMOS performance seen yet), PMOS is 51% better, which averaged to about a 30% overall pop in said currents. The contacted gate pitches are 160 nm, which continue Intel's 0.7x per generation scaling trend.   The benefits wrought by the HKMG scheme include other, even more eye-popping improvements: Mizry said gate leakage has been reduced at least 25x for NMOS and 1000x for PMOS, compared to 65 nm.   The transistor mask count at 45 nm remained the same as at 65 nm, with another mask set eliminated (no word about where that mask set was renditioned).   Mizry mentioned new high-k defect types that must be reduced or eliminated in the name of transistor reliability, including those elusive oxygen vacancies, and in true Intel fashion he announced their suppression.   As for the back end of line, the devices employ nine layers of copper interconnect, with metal-1 through metal-8 pretty standard fare, ranging in pitch size down the stack from 160 nm to 810 nm (with lower layers matched to the contacted gate pitch, upper-layer pitches increasing steadily to enhance density and perfomance), with thicknesses growing from 144 nm to 720 nm, and an aspect ratio of 1.8. But the ninth layer reflected a bit of Intel innovation inside: in order to help improve on-die power distribution, a big, thick redistribution layer was created, which is 30.5 microns thick with a 7 micron pitch, and 0.4 aspect ratio. Interconnect capacitance has been greatly reduced through aggressive scaling of the SiCN etch stop layer and other knob twisting.   He also related that that yields in the second 45-nm facility--Fab 32 in Chandler, AZ---immediately matched those of the mother fab in classic "copy exactly" fashion, with the very first lot in the desert fab coming out with the same mature-yield-level defect density results.   Mizry didn't talk about in detail about the 193-nm "dry" litho patterning or trench contacts (allegedly in the interests of time) and refused to describe the company's NMOS strain techniques when questioned about it by an attendee. But then, no Intel presentation would be complete without at least one ducked question to go with the somewhat watered-down descriptions and data.