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IEDM 2008 - 2nd Update

Articles:

1.Process varia#bility still vexing designers/ EETimes

2. 'Universal memory' race still on the starting block / EETimes

3. Toshiba 32nm CMOS Using Single Exposure Lithography

4.Flash Vendors Facing Scaling Challenges / Semiconductor International

5.IBM, Toshiba, AMD build "smallest SRAM cell" / EETimes

6.Toshiba breaks own Sonos record/ EETimes

 

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1. Process variability still vexing designers

Dylan McGrath
(12/17/2008 12:13 PM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=212500975
 
SAN FRANCISCO—CMOS device process variability remains one of the most acute problems facing the semiconductor industry, particularly at the 45-nm node and beyond, according to presenters Tuesday (Dec. 16) at the International Electron Devices Meeting (IEDM).

Random defects were the primary cause of manufacturing yield loss up to the 130-nm node, when layout systematic effects became more critical, according to a paper presented by Andrez Strojwas of Carnegie-Mellon University and PDF Solutions Inc. But more recently, Strojwas said, due to challenging product performance requirements and increased process variability, parametric yield losses have also become significant.

Strojwas's paper, "Taking the next step in Moore's Law: Design's turn to enable next technology node," prescribed a regular layout methodology for 32-nm and below, including the creation of a design fabric with a limited number of "printability friendly patterns" that enable the co-optimization of circuit, process and design. This approach calls for limited layour contacts and construct-specific rules, Strojwas said.

This methodology, known as pdBRIX, was originally developed by startup Fabbrix Inc., which was backed by Carnegie-Mellon. Fabbrix was acquired in May 2007 by PDF Solutions, which markets the technology under the name pdBRIX.

Some have argued that so-called restrictive design approaches like pdBRIX limit designers' creativity, forcing them to design within constraints established to ensure higher yield. Strojwas acknowledged this argument in his talk Tuesday, but suggested that designers' creativity is already beginning constrained by process variability's impact on yield.

Strojwas said the adoption of high-k metal gate for 32-nm would help reduce process variability, at least for one node. He said the pdBRIX methodology would enable single-pass lithography at the 32-nm node. It has been widely assumed that the 32-nm node would require double patterning lithography.

In another paper presented Tuesday, Asen Aseov from the University of Glasgow stated that the most problematic process variability issue is the statistical variability introduced by the discreteness of charge and granularity matters in transistors with features of molecular dimensions. This issue already profoundly affects SRAM design, according to the presentation. In logic circuits, it causes statistical timing problems and is increasingly leading to "hard faults," the paper stated.

"Advanced simulation of statistical variability and reliability in nano CMOS transistors," co-written by others researchers from the University of Glasgow and one from Spain's University of Santiago de Compostela, described simulation techniques for studying random dopants and reported a systemic quantum transport simulation study of atomic scale current variability.

A third paper, presented by Puneet Gupta of the University of California-Los Angeles, argued in favor of "tweakability," giving designers the flexibility to exploit power-versus-performance tradeoffs depending on use models. Transistor perturbations or tweaks that can be controlled and modeled in the electrical sense—such as gate-length biasing and transistor shaping—enable designers to improve leakage, timing and other benchmarks, Gupta argued.

"The more tweaks I have, it gives the designer the perception of a better single device, which essentially performs much better," Gupta said.

Gupta noted that tweaks of this nature would require penalties in terms of layout, characterization, modeling and physical design overhead. "Tweaks are not free," Gupta said. "But they are probably cheaper than engineering and manufacturing a new device."

Earlier, Takayasu Sakurai of the University of Tokyo presented a paper on technology/circuit collaboration for low-power LSIs. This paper argued that two recent trends for improving power efficiency in LSI systems—3D integration and ultra low voltage, or "deep sub-volt" design. To be effective, he said, both of these approaches require a concept Sakurai termed technology-circuit collaboration.

 

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2. 'Universal memory' race still on the starting block
Mark LaPedus, Dylan McGrath
(12/19/2008 1:12 PM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=212501437
 
SAN FRANCISCO -- A slew of promising ''universal memory'' technologies were disclosed at this week's International Electron Devices Meeting (IEDM) here, but don't look for mass adoption anytime soon.

At the same time, Everspin, Hynix, Infineon, IBM, Micron, Numonyx, Renesas, Samsung, Spansion, Toshiba and others are placing huge bets on one of the many candidates in what could be a ''winner take all'' game in the ''universal memory'' sweepstakes.

But economic factors, coupled with a possible slowdown in IC scaling, could once again push out the mass adoption of these ''universal' candidates, such as FRAM, MRAM, phase-change memory (PCM), programmable metallization cell (PMC), resistive RAM (RRAM) and others. "Universal memory'' implies the ability to combine the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, and the non-volatility of flash.

Some thought that many of these technologies would hit mass production or the mainstream by 2011-to-2013--or before. At that time, leading-edge flash devices are expected to hit the wall at the 22-nm node or so.

Beyond that, it could be a huge challenge to scale. The floating-gate structure is the key component of today's NOR and NAND devices, but many wonder just how long the technology will scale before running out of gas. And in DRAMs, the capacitor is close to hitting the wall, prompting the need for a new technology.

Clearly, there are signs that memory scaling could slow down, as vendors are hitting a number of roadblocks in process and design technology. ''22-nm will be delayed or pushed out,'' said Alan Niebel, chief executive of Web-Feet Research Inc. (Monterey, Calif.).

In other words, current memory technologies may live longer than expected. This in turn could slow or push out the mass adoption of universal memory types, he said.

Winners, losers

So right now, there are no clear winners or losers in the ''universal memory'' sweepstakes. Some memory types have shipped in limited volumes. Others are still waiting on the runway, leaving skeptical customers to wade through the hype.

Every year, some vendors declare that their respective ''universal memory'' products will become mainstream. But every year, most--if not all--of these products fail to live up to the hype, and, in some cases, are delayed for one reason or another.

Some say that ''universal memory'' will gain traction from 2011 to 2014. It's a moving target, but it could come down to economics, Niebel said. The eventual winner in the ''universal memory'' sweepstakes will depend on which technology will obtain the most funding, he said.

But over time, it has become painfully clear that the term ''universal memory'' is a misnomer. It's simply difficult to develop a true ''universal memory'' that can combine the attributes of DRAM and flash, he said.

As a result, the prospective products will perform some but not all functions. ''Eventually, I don't think you will call them universal memories,'' he said. ''They will be niches.''

So which technology has the lead now? Phase-change has a slight lead, while RRAM is gaining interest, he said. ''The MRAM guys will find a niche, but I'm not holding my breath,'' he added.

''PCM is closest to commercialization and by end of next year it could be competitive with NOR flash, but it'll take another few years to really get traction,'' said Gregory Wong, an analyst with Forward Insights (North York, Ontario, Canada).

''Everyone's focusing on spin-torque (STT) MRAM, but the cell sizes are still too large. It could be interesting as an embedded memory, replacing RAM and flash on a die,'' Wong said. ''RRAM is also in the early stages but companies are taking a close look at this because if you can get it into a cross-point array, with MLC or stacking cells, it could potentially replace NAND.''

Like the analyst from Web-Feet, Wong believes that next-generation memory technology will perform some but not all memory functions. For example, PCM is geared for code and code/data storage, SST-MRAM is aimed for embedded memory, and RRAM for data storage.

''As for emerging memories, I think the economic situation will force companies to look very carefully at their R&D portfolio and continue to place bets on only those technologies which have the best commercialization potential instead of taking the shotgun approach,'' he added.

At IEDM, MRAMs were hot topics. Most MRAMs write data by applying the magnetic field generated by a current running through a wire near a tunneling magnetoresistive (TMR) element to change the magnetization.

Grandis Inc. and others aim to develop and commercialize STT-RAM, a second-generation, magnetic-RAM (MRAM) technology. Grandis claims that its spin-torque transfer method uses a spin-polarized current to switch magnetic bits, a technique that is said to consume less power and enhances scalability. An STT-RAM writes data by aligning the spin direction of the electrons flowing through a TMR element.

Everspin Technologies Inc.--the MRAM spin-off of Freescale Semiconductor Inc.--has recently rolled out its first devices under its new corporate identity. Everspin (Chandler, Ariz.) has introduced a new line of 1- and 4-megabit MRAMs. As part of the new product lineup, the upstart is also debuting its first 0.13-micron MRAM--a 1-Mbit device geared for storage and other markets.

At IEDM, a paper presented by Toshiba Corp. and two Japanese universities investigated low programming current and fast switching time of a perpendicular tunnel-magneto resistance (P-TMR) for spin-transfer torque using a 50-nm P-TMR cell.

Researchers from Toshiba's corporate R&D center as well as the National Institute of Advanced Industrial Science and Technology (Tsukuba, Japan) and Tohoku University (Sendai, Japan) carried out a micromagnetic simulation based on the Landau-Lifshitz-Gilbert (LLG) equation, including the STT to reduce programming current to less than 100 uA while keeping 10-year non-volatility. Researchers used a circular P-TMR element with a diameter of 50 nm, consisting of a capping layer, a perpendicular reference layer, a magnesium oxide layer, an L1-alloy and an under layer.

The researchers repeated the measurement 200 times and claim to have recorded significantly smaller programming currents than ever reported with a comparable retention energy sigma (56 kbT). The study provided better data than any other P-TMR ever recorded, the researchers said, attributing the success to the smaller size of the P-TMR element.

The paper concludes that a p-TMR element with 50nm diameter has a low current switching of about 50uA and high speed switching time of 4 nanoseconds. The paper further concludes that P-STT-MRAM is a promising solution for high-density, non-volatile RAM.

In a second paper on MRAM, an IBM researcher described the key element of a 4-Kbit test device. The element, dubbed a magnetic tunnel junction (MTJ), is a 70- x 210-nm2 device said to have 10-year data retention cycle, a breakdown-to-voltage margin over 0.5-V and a read-induced disturbance rate of 10-9.

Like MRAM, RRAMs are gaining interest. Resistive switching memories are based on materials whose resistivity can be electrically switched between high and low conductive states.

RRAM is becoming of interest for future scaled memories because of their superior intrinsic scaling characteristics compared to the charge-based flash devices, and potentially small cell size, enabling dense crossbar RRAM arrays using vertical diode selecting elements. RRAM is seen as a potential candidate to replace conventional flash memory at or below the 22-nm manufacturing process technology node.

In order to explore the scaling limitations of conventional flash memory cells European research institute IMEC has recently started looking at resistive RAM (RRAM) cells. Five of the leading memory makers --Samsung, Hynix, Qimonda, Elpida and Micron -- are involved in the IMEC core CMOS research program and are set to share the cost and benefit from the results of the research.

At IEDM, Samsung described a ''stacked friendly all-oxide 3D RRAM. In a separate paper, a professor from Italy's Politecnico di Milano detailed work which presented a new physics-based model for resistive RAM (RRAM) reliability and programming. The researchers detailed evidence for the set operation—which restores the low-resistance state of a conductive filament—being initiated by threshold switching, a reversible transition from high to low resistance generally observed in Poole-Frenkel-controlled semiconductors.

Based on this evidence, the researchers developed analytical models for set and reset and addressed RRAM speed limitations. The research also uncovered an "over-reset" behavior, which he occurred in about 5 percent of experimental cases, which the authors said may limit the reset period. The researchers concluded that the analytical models can be used for performance and reliability prediction of RRAM under pulsed and static conditions.

A second RRAM paper by Taiwanese university researchers pointed to the promise of bi-polar switching for RRAM devices. The researchers presented a novel HfO2-based resistive memory with TiN electrodes, integrated with 0.18-micron CMOS technology. The incorporation of a thin "oxygen-getting" Ti layer as the reactive buffer enabled the device to achieve excellent memory performance, including low operation current (down to 25 uA), an on/off resistance ratio above 1,000, switching speeds of 5 nanoseconds, switching endurance of better than 106 cycles and data retention of 10 years to 200 degrees Celsius, according the paper.

The researchers from Taiwan's Industrial Technology Research Instititue, MingShin University of Science & Technology and National Tsing Hua University, concluded that the device they created is a promising candidate for application in next generation non-volatile memory.

And not to be outdone, there's phase-change. This technology--sometimes called ovonic unified memory (OUM)--dates back to 1970, when it was announced by Energy Conversion Devices Inc.

OUM is one of many efforts based on phase-change technology, which received considerable attention at IEDM. The technology is based on the electrically induced phase change of chalcogenide materials, which have been difficult to manufacture reliably in volumes. Phase-change materials have both crystalline and noncrystalline states that can represent "0" or "1," and it's possible to toggle between them by applying a small reset current.

Numoynx B.V. claims that it has officially shipped its PCM device commercially this week. Numonyx has finally shipped phase-change memory products amid some delays, after introducing the device last year.

That device, codenamed ''Alverstone,'' is a 90-nm, 128-Mbit part. Going forward, Numonyx is skipping the 65-nm node for the next device and moving "as quickly as possible" to the 45-nm node.

Numonyx (Rolle, Switzerland) is the memory spin-off of Intel Corp. and STMicroelectronics Inc. STMicroelectronics holds about a 49 percent stake in Numonyx, Intel has 45 percent, and Francisco Partners owns 6 percent.

At IEDM, Samsung described a ''unified 7.5-nm dash-type confined cell for PCM. IBM also had a paper on the subject.

Others are developing rival technologies. At IEDM, Toshiba Corp. broke its own record. Last year, Toshiba claimed that it had developed a new double tunneling junction layer technology, enabling memory devices with densities of over 100 gigabits in the 10-nm node generation.

Recently, the company showed a 15-nm device. This year, it demonstrated 10- and 8-nm memory devices. All devices deployed a double tunnel layer, based on a Sonos (silicon oxide nitride oxide semiconductor) type device structure. Sonos is a memory structure that holds electrons in the nitride layer in the gate insulator.

Toshiba showed that a 10-nm gate length bulk-planar Sonos-type memory device retains 2.6 decades memory window for 10 years in less than 13- V w/e voltages.

An 8-nm device shows the same performance. The structure sandwiches a 1.1-nm silicon nanocrystals layer between the 1-nm thickness oxide films.

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3. Toshiba 32nm CMOS Using Single Exposure Lithography

 

18 Dec, 2008

TOKYO-- Toshiba Corporation (TOKYO: 6502) today announced a cost-effective 32nm CMOS platform technology that offers higher density and improved performance while halving the cost per function from 45nm technology. The platform was achieved by application of advanced single exposure lithography and gate-first metal gate/high-K process technology. This technology enables a 0.124μm2 SRAM cell and a gate density of 3,650 gate/mm2. This SRAM cell is the smallest yet achieved in the 32nm generation. The platform technology is based on a 32nm process technology developed jointly with NEC Electronics Corporation.

Advanced semiconductor process migration faces challenges to achieve both cost competitiveness and enhanced performance for stricter design rules. This requires innovative technological optimization in lithography and patterning integration, materials, and device design.

Realizing the strict design rule in the 32nm generation was originally seen as requiring dual exposure technology in the lithography process, which would result in higher process costs due to increased process steps, and in degraded manufacturing yields owing to increased process dusts. Toshiba realized an architecture based on single exposure lithography by applying ArF immersion lithography with a NA 1.3 and over, and by optimizing the lithography illumination conditions.

The development work also demonstrated that application of a metal gate/high-K not only boosts transistor performance but also reduces threshold voltage mismatch, which affects stable operation of SRAM and logic circuits. In addition, a bent-shaped type cell was selected for layout optimization, which also contributed to reduce threshold voltage mismatch.

By adopting this approach, Toshiba realized a 32nm CMOS platform design that reduces cost per function by 50% from 45nm technology, an achievement that would have been impossible with conventional poly/SiON and double patterning.

Toshiba will further enhance development of the new platform.

The achievement was introduced today at the International Electron Devices meeting (IEDM) in San Francisco, CA.

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4.Flash Vendors Facing Scaling Challenges

 

David Lammers, News Editor -- Semiconductor International, 12/23/2008 9:27:00 AM

With flash memory scaling coming under increasingly sharp questioning, Toshiba Corp. (Tokyo) researchers said they have developed a double tunnel layer technology for SONOS-type memories that could be scaled to the 10 nm generation.

At the recent International Electron Devices Meeting (IEDM) in San Francisco, Toshiba engineers described a double tunnel oxide structure which can boost densities to >200 Gb at the 10 nm node. “The technology also has the potential for use at higher densities in even smaller nodes,” said Toshiba spokesman Keisuke Ohmori.

The Toshiba engineers adapted a silicon oxide nitride oxide semiconductor (SONOS) structure, which retains electrons in a nitride layer formed inside the gate insulator. The double tunneling layer structure sandwiches an ultra-thin, 1.1 nm silicon nanocrystal layer between 1 nm thick oxide films.

Toshiba described a double layer SONOS structure at IEDM.

Compared to today’s floating gate structures, the Toshiba spokesman said the SONOS approach “is better suited for scaling due to a thinner tunnel layer and a charge transfer mechanism that would not cause current leakage.”

Toshiba said low electric fields present challenges for the 10 nm node.

At the 2007 IEDM, Toshiba presented a SONOS-type memory with a 1.2 nm silicon nanocrystal layer capable of supporting 100 Gb densities at the 15 nm generation. For the 10 nm generation memory cell described this year, the distance between the silicon substrate and the gate is longer than the memory cell size itself. That increases the difficulty of the write and erase functions because the low electric field in the tunnel layer slows the movement of electrons, due to the 2-D effect. Overcoming that required optimization of the tunnel layer, he said.

An interesting admission

t IEDM, flash memory pioneer Stefan Lai said floating gate flash faces significant scaling challenges. Lai, who developed the EPROM tunnel oxide structure used in the first NOR flash products sold by Intel, said the regular structure of both NOR and NAND flash means that “lithography still has some room to go.”

However, the number of stored electrons is declining to perilously small numbers. “When I started in this industry, each bit was represented by hundreds of thousands of electrons. In terms of charge loss, we could afford to lose one electron a day. Now, with a bit represented by multiple tens of electrons, if you lose, say, one out of 20 electrons, it won’t take many days for the bit to fail,” Lai said in a keynote speech at IEDM.

He advocated development of phase change memories (PCMs), partly because they do not require that the bit be erased before the write function. Besides their direct-write capability, PCMs can be created with a separate RAM array supporting a denser storage array for solid-state drive (SSD) functions.

“The scaling of PCMs is limited by the materials,” Laid said, noting that IBM researchers have demonstrated 5 nm PCM layers that appear to work. “It is a materials challenge, and I’ll be honest and say that we still don’t know enough about the operating window of these materials. And testing will be difficult. It will require new learning by the industry.”

Lai, who left Intel to work for a short time at phase change memory technology provider Ovonyx Inc. before recently going independent, made an interesting admission in the course of his IEDM speech. With his mindset accustomed to developing chips with high levels of reliability and bit stability, Lai said he studied NAND flash technology in the late 1980s and rejected the concept. Fujio Masuoka, the Toshiba engineer who first proposed NOR flash in 1984, went on to develop serial NAND technology, first announced in 1987.

In his IEDM keynote last week, Lai said 20 years ago the bit error rate (BER) of NAND appeared to be too high. Soon after, NAND vendors showed that by using system-level error correction techniques -- similar to those used by the hard disk drive industry -- that NAND could be made reliable. The result, he noted, is a roughly $20B NAND industry in 2008.

“My conclusion at the time was that NAND does not work. That was a bad call. But it was based on my definition of acceptable bit error rates,” Lai said, adding that the decision shows how engineers must examine the experiential framework within which their decisions are made.

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5.IBM, Toshiba, AMD build "smallest SRAM cell"

John Walko
(12/17/2008 6:35 AM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID212500850
 
LONDON — Toshiba, IBM and AMD have developed what they says is the smallest functional SRAM cell that makes use of FinFETs. The trio outlined details of the cell at this week's International Electron Devices Meeting in San Francisco.

The cell, developed with a high-k/metal gate (HKMG) material, has an area of 0.128µm2, is said to have significant advantages over planar-FET cells for future technology generations.

The collaborators optimized the processes — especially for depositing and removing materials — including HKMG from vertical surfaces of the non planar FinFET structure.

The researchers also say the design is likely to scale to the 22-nm node or beyond, and that the nonplanar-FET SRAM cell is more than 50 percent smaller than the 0.274¼m2 such cell previously reported.

The trio also investigated the stochastic variation of FinFET properties within the highly scaled SRAM cells and simulated SRAM cell variations at an even smaller cell size. They verified that FinFETs without channel doping improved transistor characteristic variability by more than 28 percent.

In simulations of SRAM cells of 0.063¼m2 area, equivalent to or beyond the cell scaling for the 22nm node, the results confirmed that the FinFET SRAM cell is expected to offer a significant advantage in stable operation compared to a planar-FET SRAM cell at this generation.

 

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6.Toshiba breaks own Sonos record

Mark LaPedus
(12/16/2008 5:14 PM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=212500780
 
SAN FRANCISCO -- At this week's International Electron Devices Meeting (IEDM) here, Toshiba Corp. will break its own record.

 

Last year, Toshiba claimed that it had developed a new double tunneling junction layer technology, enabling memory devices with densities of over 100 gigabits in the 10-nm node generation.

Recently, the company showed a 15-nm device. This year, it demonstrated 10- and 8-nm memory devices. All devices deployed a double tunnel layer, based on a Sonos (silicon oxide nitride oxide semiconductor) type device structure. Sonos is a memory structure that holds electrons in the nitride layer in the gate insulator.

Toshiba showed that a 10-nm gate length bulk-planar SONOS-type memory device retains 2.6 decades memory window for 10 years in less than 13- V w/e voltages.

An 8-nm device shows the same performance. The structure sandwiches a 1.1-nm silicon nanocrystals layer between the 1-nm thickness oxide films.

 

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