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IEDM 2008 Preview

Articles:

1.IEDM Preview: Focus turns to 32 nm and beyond/ EETimes

2. Intel to extend high-k lead at IEDM / EETimes

3.Intel completes 32nm process development/ DigiTimes

4.IEDM Courses and Program

 

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1. IEDM Preview: Focus turns to 32 nm and beyond

Don Scansen
(12/10/2008 1:04 PM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=212400168
 

OTTAWA — With 32-nm process technology less than a year away from entering production, both Intel Corp. and IBM Corp. will provide details about their technologies during the 2008 IEEE International Electron Devices Meeting in San Francisco. IEDM also will offer a glimpse down the semiconductor roadmap, including the 22-nm production node.

As for 32 nm, Intel will present details of its technology first announced in September 2007 at the Intel Developer Forum. Sanjay Natarajan, manager of Intel's 32-nm CMOS technology development, demonstrated a fully functional 291-Mbit SRAM test chip. Intel will update it progress in 32-nm development at IEDM.

Intel's 32-nm process continues on the path laid down with the introduction of the high-k metal gate stack at 45 nm. The second-generation high-k dielectric is scaled down to improve transistor performance while aiding SRAM scaling. Intel also dives into immersion lithography at 32 nm.

Intel claims world records for drive current and gate pitch. The NMOS drive current is 1.55mA/m, or about a 14 percent improvement over 1.36mA/m at 45 nm.

The 32-nm process achieves about 70 percent linear scaling to reach the best reported gate pitch of 112.5 nm, thereby keeping Moore's Law on track. The gate pitch cited in Intel's IEDM paper is actually a 3-percent shrink from their first SRAM test chip. That shrink also enabled an SRAM cell size reduction from 0.182 down to the 0.171 microns2, something Natarajan will describe at IEDM.

Intel Senior Fellow Mark Bohr said he remains confident that Intel's 32-nm process will be ready for volume production during the fourth quarter of 2009, although ramp up ultimately depends on when microprocessor product managers switch to the next node.

Given its track record, it wouldn't be surprising if Intel's 32-nm technology was delayed beyond the end of 2009. That would be two years after 45 nm arrived, maintaining the sequence of Intel's process node introductions.

An Steegen, IBM's manager for 32-nm bulk technology Development, will present details of its 32-nm foundry technology. IBM will offer both a low-power, high-performance flavor of their 32-nm bulk process. IBM first unveiled a low-power 32-nm technology on silicon-on-insulator at the VLSI Symposium earlier this year. With IBM's shift to a high-k metal gate process, Steegan and her team will focus on scaling and optimizing both effective electrical thickness of the gate dielectric as well as the physical gate length.

In the low-power version of IBM's 32-nm bulk process, no strain engineering techniques were used. In the high-performance process, standard stressors enhanced the baseline transistor. Actual transistor performance metrics of the drive current and leakage will be presented during IEDM.

IBM's 32-nm team is quick to point out that their gate-first approach to high-k continues conventional design rules for the physical design of circuits. Foundry customers will not be faced with restrictions on design rules. The gate-first high-k stack takes advantage of the maturity of polysilicon gate processing while introducing advanced materials to improve transistor performance.

IBM's process also uses a single metal gate with different interface layer materials to set the workfunction for NMOS and PMOS transistors.

IBM said it expects the market to develop earlier for the low-power version of its 32-nm bulk process. Therefore, it plans to have it ready for production late in 2009. The high-performance version with strained silicon won't arrive until 2010. IBM is running multiproduct wafers now, and expects to get silicon into the hands of customers in February.

Taking a longer view of the semiconductor roadmap, IBM will announce at IEDM what it claims in the world's smallest reported SRAM cell size: 0.1 microns2. Bruce Doris, IBM's manager of device integration research at Albany Nanotech, said the device also is "an important proof-of-concept that planar CMOS technology using conventional techniques can produce working SRAM at 22 nanometers."

Although the 22-nm team hopes to push conventional tungsten contact plugs as far as possible, their cell was built using damascene copper contacts. The researchers are also investigating both copper and tungsten contact approaches, but the copper contact process was ready in time to create the demonstration devices.

IBM's SRAM layout demanded a contact window of only 25 nm to match its 25-nm gate lengths.

The Albany group provided early research for IBM's process development teams in East Fishkill, N.Y. The 22-nm research chips were made using production 300-mm tools at Albany Nanotech. Doris claims his team has produced even smaller SRAM bit cells.

Intel Fellow Kelin Kuhn will teach one module of an IEDM short course, "22-nm CMOS Technology." Kuhn will provide her insights into 22-nm device architecture and performance elements.

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2. Intel to extend high-k lead at IEDM
Mark LaPedus
(12/10/2008 12:01 AM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=212300580
 
SAN JOSE, Calif. -- At next week's International Electron Devices Meeting (IEDM) in San Francisco, Calif., Intel Corp. is expected to extend its lead over AMD, IBM and other microprocessor vendors in the high-k/metal-gate race.

In a paper, Intel (Santa Clara, Calif.) will describe a new 45-nm derivative for system-on-a-chip (SOC) designs based on high-k/metal-gate technology. In addition, the chip giant will provide more details about its previously-announced, 32-nm process, based on a second-generation, high-k/metal-gate architecture. And, Intel will talk about a quantum well field effect transistor technology.

It is also working on its 22-nm technology, which is in R&D. While it did not elaborate on this technology, the company acknowledged that it may end up processing its 22-nm designs using 193-nm immersion scanners, meaning extreme ultraviolet (EUV) lithography is late to the party--again.

Regarding two other key technologies--high-k and metal-gates--a big question remains: Can Intel's competitors catch up? To date, Intel's main rival, Advanced Micro Devices Inc. (AMD), has announced its 45-nm processors, but the devices reportedly do not use a high-k/metal-gate scheme.

AMD's technology partner, IBM Corp., does not expect to have its high-k/metal-gate solution until the 32-nm node, reportedly causing some angst in the market. IBM's ''fab club'' is using a gate-first approach to high-k and metal gates, while Intel is deploying a rival replacement-gate technology.

For some time, Intel has already shipped 45-nm processors based on the technology, giving it an edge in the market. High-k and metal gates are key building blocks for scaling and reducing the leakage within the critical gate stack, enabling the next-generation transistor.

High-k uses a material called hafnium to replace the transistor's silicon dioxide gate dielectric, which is running out of gas in today's designs. Also on the transistor, a metal material replaces the polysilicon gate electrode of NMOS and PMOS structures.

Despite an endless parade of claims made by vendors, high-k/metal-gate technology is much harder to develop than previously thought. IBM's ''fab club'' is reportedly wrestling with the technology, while the foundries will not deploy the scheme until the 32- or 28-nm nodes.

With the exception of Intel, ''nobody else is shipping high-k yet,'' said Mark Bohr, Intel senior fellow and director of process architecture and integration. ''We have more than a one generation lead in technology,'' Bohr told EE Times.

At IEDM, Intel will present several papers on the subject, including at 32-nm. As far back as late-2007, the chip giant rolled out its initial 32-nm test chip. The device has a 0.171-micron2 cell size containing more than 1.9 billion transistors.

Then, in October of 2008, the company tipped its 32-nm process. As reported, the process incorporates copper interconnects, a second-generation high-k/metal-gate technology and a fourth-generation strained-silicon scheme.

Intel is expected to deploy its first immersion lithography scanners at 32-nm. The 193-nm machines will be sole sourced from Nikon Corp. (Tokyo).

The transistors feature dual band-edge workfunction metal gates and high-k gate dielectrics with an equivalent oxide thickness (EOT) of 9-nm or 9 angstroms. In comparison, the company's 45-nm high-k designs have an EOT of 10-nm. The 32-nm version enables Intel to reduce transistor variability,'' Bohr said.

At 32-nm, Intel's transistor gate pitch is 112.5-nm. Intel's 32-nm logic technology provides about 70 percent linear feature size scaling and 50 percent area scaling, as compared to the company's 45-nm process. In addition, the process enables the highest drive currents reported to date for 32-nm technology.

Intel is on track for 32-nm production readiness in Q4 2009. Meanwhile, the company is also working on its 22-nm process. The technology will make use of 193-nm immersion scanners with either double-patterning or computational lithography techniques, he said. For 22-nm, EUV ''probably won't be ready,'' he said.

At IEDM, meanwhile, Intel will describe a new 45-nm process derivative for SOCs. The process is still in the lab, but it could propel a new and important business for the chip giant.

Last year, Intel created a new SOC enablement group. Intel has stated it has at least four SoCs in the works for systems outside its traditional PC markets. Tolapai is aimed at storage networks, Silverthorne at handhelds, Larabee at high-end visualization systems and Canmore at wired consumer devices.

On the process front, the 45-nm SOC technology makes use of a high-k/metal-gate scheme that has been ''optimized for low power products,'' he said.

Within the process, the PMOS/NMOS logic transistor drive currents are 0.68/1.04 mA/um, respectively, at 1.1-Volt and offstate leakage of 1 nA/um. High voltage I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OPT fuses are employed.

And not to be outdone, Intel will demonstrate for the first time a high-speed, low-power quantum well field effect transistor. The p-channel structure will be based on a 40-nm indium antimonide (InSb) material, which is said to achieve a cut-off frequency (fT) of 140-GHz at a supply voltage of 0.5 V.

Transistors made on III-V materials are being explored in research as a means to provide improved performance and low power capabilities beyond what silicon may be able to provide.

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3.Intel completes 32nm process development

Press release, December 10; Joseph Tsai, DIGITIMES [Wednesday 10 December 2008]

Intel has completed the development phase of its next-generation manufacturing process that further shrinks chip circuitry to 32nm. The company is on track for production readiness in the fourth quarter of 2009.

Intel said it will provide technical details around the 32nm process technology along with several other topics during presentations at the International Electron Devices meeting (IEDM) next week in San Francisco.

One paper and presentation will describe a logic technology that incorporates second-generation high-k + metal gate technology, 193nm immersion lithography for critical patterning layers, and enhanced transistor strain techniques. These features enhance process performance and energy efficiency, said Intel. Intel also claimed that its manufacturing process has the highest transistor performance and the highest transistor density of any reported 32nm technology in the industry.

Other Intel IEDM papers will describe a low power SOC version of Intel's 45nm process, transistors based on compound semiconductors, substrate engineering to improve performance of 45nm transistors, integrating chemical mechanical polish for the 45nm node and beyond, and integrating an array of silicon photonics modulators. Intel will also participate in a short course on 22nm CMOS Technology.

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