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IEDM 2010

Articles:

1. 2010 IEDM Full Technical Program / IEEE International Electron Devices Meeting

2. IEDM to feature 3-D chips, carbon nanotubes, FinFETs /EETimes

3. IBM Alliance simplifies pFET HKMG /electroiq.com

4. IM Flash details 25nm NAND/electroiq.com

5. Carbon nanotube vias approach production densities /electroiq.com

 

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1. 2010 IEDM Technical Program


Select sessions below to view online, or download Full 2010 IEDM Technical Program (PDF version) (419 KB)

Plenary Session

Session 2: Process Technology - Advanced 3D Integration

Session 3: CMOS Devices and Technology – Ultra-Thin Body Transistors and Device Variability

Session 4: Characterization, Reliability, and Yield – Front End of Line (FEOL) Reliability

Session 5: Memory Technology – Flash Memory

Session 6: Quantum Power and Compound Semiconductor Devices – Next Generation Digital Devices

Session 7: Displays, Sensors, and MEMS – MEMS Resonators

Session 8: Modeling and Simulation – High-Frequency and Multi-Gate Device Modeling

Session 9: Solid-State and Nanoelectronic Devices – CNT, MTJ, Devices and Nanowire Photodiodes

Session 10: CMOS Devices and Technology – CMOS Performance Enhancing and Novel Devices

Session 11: Process Technology - Channel Engineering and High-k Technology

Session 12: Memory Technology – IT and Magnetic RAM

Session 13: Emerging Technologies – Next Generation Power Devices and Technology

Session 14: Displays, Sensors, and MEMS – Image Sensors

Session 15: Modeling and Simulation – Challenges in Advanced Device Performance and Variation Modeling

Session 16: Solid-State and Nanoelectronic Devices – Low-Power and Steep Slope Switching Devices

Session 17: Device Circuits

Session 18: Process Technology – Advanced Technologies for Ge MOSFETs and New Concept Devices

Session 19: Memory Technology – Resistive RAMs

Session 20: Quantum Power and Compound Semiconductor Devices – Advanced Power Devices and Reliability

Session 21: Display, Sensors, and MEMS – Thin Film Transistors

Session 22: Modeling and Simulation – Simulation of Memory Devices

Session 23: Solid-State and Nanoelectronic Devices – Graphene Devices

Session 24: 2010 IEDM Evening Panel Discussion

Session 25: 2010 IEDM Evening Panel Discussion

Session 26: Process Technology – Advanced Source/Drain and Channel Engineering

Session 27: Memory Technology – 3D CMOS Devices and Technology – Advanced High-k Metal Gate SoC and High Performance CMOS

Session 28: Characterization, Reliability, and Yield – RTN and Memory

Session 29: Memory Technology – Phase Change Memory and 3-Dimensional Memory

Session 30: Quantum, Power, and Compound Semiconductor Devices – Ultra High Speed Transistors

Session 31: Displays, Sensors, and MEMS – PV and Energy Harvesting

Session 32: Modeling and Simulation – Simulation of Non-Silicon Materials and Devices

Session 33: Process Technology – Novel Process Technologies

Session 34: CMOS Devices and Technology – Advanced FinFETs and Nanowire FETs

Session 35: Characterization , Reliability, and Yield – Back-end SRAM and ESD Reliability

Session 36: Displays, Sensors, and MEMS – Biosensors and MEMS

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2. IEDM to feature 3-D chips, carbon nanotubes, FinFETs

SAN JOSE, Calif. - The IEEE International Electron Devices Meeting (IEDM) is almost here.
Mark LaPedus 9/20/2010 5:23 PM EDT


At the event, look for papers on 3-D chips, carbon nanotubes, FinFETs, MEMS, NAND and other topics. The event will be held in San Francisco from Dec. 6-8. Here's a sample of the papers:      

On the logic side, TSMC will unveil a 22-/20-nm CMOS technology. It features FinFET transistor architectures, 193-nm immersion lithography, SiGe stressors, metal gates and high-k dielectrics. The FinFETs are built with dual-epitaxy and multiple stressors.

N-/P-channel on-current is 1200/1100µA/µm respectively, while off-current for both N and P versions is 100nA/µm, according to TSMC. The researchers used the new technology to build a dense 0.1µm2 SRAM memory cell, which had noise characteristics (90mV noise margin) even at a low 0.45V operating voltage, according to the silicon foundry giant.

In a competing technology, a team led by CEA LETI in France will say it grew double- and triple-walled carbon nanotubes with 4-5-nm diameters using a root-growth process. The work represents a significant step toward implementation of carbon nanotube vias, according to the group.

3-D chip design appears to be a theme as well. Through-silicon vias (TSVs) are holes running vertically through the stack, filled with metal that interconnects all the levels. At the IEDM, a team led by Universitie de Savoie in France will report that although 4µm-wide copper TSVs did electrically couple with adjacent 65-nm NMOS transistors to produce a spike in static drain current, no variation in their operation in a test circuit (a ring oscillator) was seen.  

In another logic effort, a team led by University of Tokyo will announce an InGaAs MOSFET built on an insulating substrate, and also the thinnest InGaAs MOSFET ever made, with a 3.5-nm channel. Nonconducting substrates are key to the eventual integration of such devices with silicon CMOS architectures because they reduce short-channel effects.

On the memory front, researchers from Intel Corp. and Micron Technology Inc. will talk about a 25-nm 64-Gbit multi-level cell (MLC) NAND memory, with a small cell size of 0.0028µm2.  The half-pitch of the cell is 24.5-nm in the word line direction and 28.5-nm in the bit line direction.

In MEMS, University of Denver researchers will describe a fully micromechanical oscillator that makes use of inter-related piezoresistive, thermal and mechanical effects to render it capable of self-sustained oscillation without the need for supporting electronic circuitry, whether under vacuum or in atmospheric pressure. The oscillators are capable of achieving frequencies as high as 6.6MHz, consume only milliwatts of power, achieve output voltage amplitude as high as 825mV, and consist of simple-to-fabricate silicon structures.

And not to be outdone, a paper from Purdue will describe the modeling and simulation of nanoscale devices with the goal of producing a low-cost, high-throughput lab-on-a-chip to detect DNA, proteins and other electrically charged biomolecules in blood and other electrolyte solutions.

 

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3. IEDM preview: IBM Alliance simplifies pFET HKMG


by Laura Peters, contributing editor

October 18, 2010 - Researchers from the IBM Alliance have developed a new germanium ion implantation process that implants Ge into the shallow silicon channel region prior to high-k/metal gate (HKMG) stack depositions. The process allows superior low threshold voltage (Vt) modulation relative to aluminum or titanium caps for low-Vt pFETs. At the 16nm node, such an approach could eliminate an aluminum cap and solve the low-Vt problem. Ion implantation also overcomes the integration challenges associated with epitaxial SiGe channel formation, which requires hardmask integration and precise silicon recess and SiGe thickness control. The group that developed the process, from Toshiba America Electronic Components, IBM's Semiconductor Research and Development Center, and STMicroelectronics in Albany, NY, will present their findings at International Electron Devices Meeting (IEDM) in San Francisco, CA (Dec. 6-8).

To achieve low-Vt modulation, the researchers compared aluminum to germanium channel ion implantation processes. The Ge implant was followed by a recrystallization anneal, interfacial layer formation, then HKMG deposition. undesirable hump in the C-V curve could be eliminated, the group determined, by using a cryogenic process in which wafer temperature was reduced during implantation. The Ge implant proved superior to the aluminum process because it lowered threshold voltage by as much as 500mV with no increase in equivalent oxide thickness (EOT, see figure below). Conversely, large degradations of EOT occurred with the aluminum ion implantation. Other electrical results were favorable including an improved gate leakage current density/EOT curve (Jg-EOT), low gate-induced drain leakage (GIDL) current, and slightly improved NBTI characteristics over the control.

Threshold voltage shift vs. EOT.
Threshold voltage shift vs. EOT. The germanium channel ion implantation induced ~500 mV threshold voltage shift with no increase in inversion thickness. The aluminum ion implant provides large Vt shift but also large EOT degradation. (Source: IBM Alliance)



To better optimize the process, the researchers sought to determine the physical cause of the threshold voltage modulation. Backside SIMS revealed high Ge concentration near the gate stack/silicon interfaces, and the threshold voltage shift correlates well with the germanium peak concentration. Through a process of elimination and chemical analysis, they determined that pile-up of Ge atoms at the interfacial layer/channel interface determines the pFET threshold voltage shift. This physical cause of Vt modulation is completely different than that of a conventional epitaxial SiGe

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4. IEDM preview: IM Flash details 25nm NAND


by Laura Peters, contributing editor

October 18, 2010 - At the upcoming International Electron Devices Meeting (IEDM, 12/6-8 in San Francisco, CA), Intel and Micron researchers will reveal the key process advances and electrical results behind their multilevel cell (MLC), 64Gb NAND flash memory technology. At the start of 2010 their joint venture, IM Flash, said it was planning to ramp production of its 3bits/cell 64Gb NAND flash by year's end.

In this 25nm device, aggressive scaling in both the word line and bit line directions increases word line-word line capacitance as well as cell-cell interference. Half pitches of only 24.5nm between word lines and 28.5nm between bit lines allowed a cell size of 0.0028μm2. The researchers used air gaps (see figures) to reduce total interference by 25% and bit line capacitance by 30%. They also optimized the insulating tunnel oxide and inter-poly dielectric of the cell as well as surrounding dielectric to minimize leakage and charge trapping.

NAND cell in the word line direction.  Bitline half pitch is only 28.5nm
NAND cell in the word line direction shows the select gate and contacts. Air gaps reduce cell-cell and word line-word-line capacitance. (Source: Micron Technology/Intel) Bitline half pitch is only 28.5nm, requiring air gaps to reduce bit line-bit line capacitance. (Source: Micron Technology/Intel)


Another consequence of intense scaling is the effect on dopant fluctuation. The researchers note that at 25nm, threshold voltage can be expected to vary by ~30% due to random dopant fluctuation. This is countered by additional optimization of programming algorithms to achieve multilevel cell performance comparable to previous generations including its predecessor, the 34nm 32Gb technology.

The small die size of the 64Gb NAND flash allows packaging in a standard TSOP.

In January, IM Flash was reportedly leading the NAND flash race with 25nm technology among contenders Samsung, Toshiba, Hynix, and others. Elpida (and Spansion) plans to start shipping samples of 1.8V 4Gb NAND flash memory during 4Q10, and will begin mass production during the first quarter of 2011.

The industry is gradually making a transition from 2-bit multilevel cell to 3-bit technology (X3). Earlier this year, SanDisk chairman/CEO Eli Harari told SST that from 2010-2013, he sees the transition from MLC to X3 for about 50% of NAND bits. For SanDisk, X3 provides more than 20% more die per wafer compared to standard MLC memory on the same technology node.

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5.IEDM preview: Carbon nanotube vias approach production densities



by Laura Peters, contributing editor

October 20, 2010 - Researchers will soon report they are close to achieving the density of (CNTs) needed to manufacture carbon nanotubesinterconnect vias for production applications.

At the upcoming International Electron Devices Meeting (IEDM, 12/6-8 in San Francisco, CA), a group from Grenoble, France-based CEA LITEN and CEA LETI, École Polytechnique Fédérale Lausanne in Switzerland, and the UK's Cambridge University will present its methods used to achieve vias with a density of 2.5 × 1012 tubes/cm2 -- equivalent to 8 × 1012 walls/cm2, nearing the value of 3 × 1013 walls/cm2 required for interconnect vias. This density is an order of magnitude beyond the previous state of the art.

Carbon nanotubes are ideal as interconnect vias because they can carry currents of over 108 A/cm2. However, there are two key challenges preventing CNT incorporation in interconnect vias: reaching the necessary density and having a viable integration scheme. These researchers grew CNTs on metal alloy (99.5% aluminum, 0.5% copper) or polysilicon substrates using an iron catalyst. The AlCu alloy was chosen due to its low resistance at very small linewidths. Using a root-growth method at 580°C, 200mm wafers, and the process flow shown in Figure 1, the result was double- and triple-walled CNTs with via geometries from 250nm to 1μm (Figure 2).

Figure 1. Process flow for CNT fabrication: wet etch is followed by catalyst deposition, CNT growth, encapsulation with Al2O3 by ALD, CMP, then top contact. (Source: CEA/École Polytechnique/Cambridge U.)



To measure the density achieved, the researchers dipped the CNTs in alcohol, yielding a filling factor as high as 64%. The group was also able to measure the density as a function of via diameter, which varied from 5 × 1012 to 8 × 1012 walls/cm2.

Cross-section of a 250nm CNT via on AlCu after CMP. High-density CNT growth in 500nm vias on AlCu line.
Cross-section of a 250nm CNT via on AlCu after CMP. (Source: CEA LITEN)
High-density CNT growth in 500nm vias on AlCu line. (Source: CEA LITEN)

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