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IEDM 2011


1. 2011 IEDM Technical Program/ IEEE International Electron Devices Meeting

2. IEDM: IMEC reports 10-nm RRAM cell /EETimes

3. IEDM: SuVolta transistor operates down to 0.4-VIEDM: SuVolta transistor operates down to 0.4-V /EETimes

4. IBM, Micron to build hybrid memory with TSVs / EETimes



1.2011 IEDM Technical Program

Select sessions below to view online, or download PDF version (419 KB).

Plenary Session

Session 2: Nano Device Technology – Graphene and Nano Optical Devices

Session 3: Memory Technology – PCM and RRAM

Session 4: Circuit and Device Interaction – Emerging Devices and Circuits Beyond CMOS

Session 5: Modeling and Simulation – Variability and Steep Sub-threshold of Slope Devices

Session 6: Characterization, Reliability, and Yield – Nanoscale Characterization, Circuits, and 3D-Integration

Session 7: Process Technology – 3D, Heterogeneous Layer Integration, and Self-Assembly Patterning

Session 8: Displays, Sensors, and MEMS – Image Sensors

Session 9: Memory Technology – Flash Memories

Session 10: Emerging Technologies – Energy Harvesting Devices, Circuits and Systems

Session 11: Modeling and Simulation – Graphene Devices and Ultimate Logic Architectures

Session 12: Characterization, Reliability, and Yield – Memory Reliability

Session 13: Quantum, Power, and Compound Semiconductor Devices – Planar In Ga As FETs

Session 14: Displays, Sensors, and MEMS – Novel Thin Film Transistor Technology for Large Area Electronics

Luncheon Session

Session 15: Circuit and Device Interaction – Platform Technology and Design Optimization

Session 16: Nano Device Technology – New Concept Devices and Advanced Group IV MOSFETs

Session 17: Modeling and Simulation – Simulation of Memory Devices Devices and 3D LSIs

Session 18: Characterization, Reliability, and Yield – High-k/Metal Gate Reliability

Session 19: Quantum, Power, and Compound Semiconductor Devices – GaN Devices

Session 20: Displays, Sensors, and MEMS – Resonators and RF MEMS

Session 21: Tuesday Evening Panel Session

Session 22: Tuesday Evening Panel Session

Session 23: Nano Device Technology – Carbon Nano-tubes and Si-nanowire Devices

Session 24: Memory Technology – RAM and Specialty Memories

Session 25: Circuit and Device Interaction – Low Voltage Design and Device Variability

Session 26: Quantum, Power, and Compound Semiconductor Devices – Power Devices and Applications

Session 27: Characterization, Reliability, and Yield – MOSFET Reliability – BTI, Mobility and Noise

Session 28: Process Technology – Dual Channel CMOS and Gate Stack Materials

Session 29: Displays, Sensors, and MEMS – MEMS and Energy Harvesters

Session 30: Nano Device Technology – Atomic Switch, Quantum Transport and Alternative Nanodevice Applications

Session 31: Memory Technology - RRAM

Session 32: Circuit and Device Interaction – Advanced SRAMs

Session 33: Quantum, Power, and Compound Semiconductors Devices– Novel III-V FET Architectures

Session 34: Modeling and Simulation – Simulation Methodologies for Advanced Devices and Technologies

Session 35: Process Technology – High Mobility Channel and Junction Technology

Session 36: Displays, Sensors, and MEMS – Biosensing and Solar Conversion



2.IEDM: IMEC reports 10-nm RRAM cell

Peter Clarke

12/8/2011 6:54 AM EST

LONDON – European research institute IMEC has reported a Resistive RAM (RRAM) memory cell that measures 10-nm by 10-nm at the International Electron Devices Meeting, which took place Dec. 5 to 7 in Washington DC. The organization claims this is the smallest such cell and that it shows the potential to replace NAND flash memory.

RRAM is one of a number of emerging non-volatile memory technologies being researched as a potential replacement for NAND flash, which is based on charge-storage and which in its present form is thought will not scale below about 18-nm planar dimensions.

RRAM is based on the electronic switching of a resistor element material between two stable resistive states and can be contained in a cross-bar array. IMEC has focused on hafnium/hafnium-oxide as the switching material sandwiched between conventional titanium-nitride contacts.

Cross-section of 10-nm Hf/HfOx RRAM element. 

The major strengths of RRAM technology, sometimes also labeled as memristor, are its potential density due to cross-bar formation and speed. IMEC researchers have previously stated that they feel they have a good understanding of the filamentary switching mechanism based on the movement of oxygen vacancies in the material.

The reported Hf/HfOx resistive stack has an area of less than 10-nm x 10-nm (100 square nanometers) and has demonsrated an endurance of more than 10^9 (1 billion) cycles. It has nanosecond on/off switching times at low voltages and a resistive window of a factor 50 that shows no closure after functioning at 200 degrees C for 30 hours, IMEC said. This gives an exprapolated data retention of 10 years at 100 degrees C.

The switching energy per bit is below 0.1pJ, and AC operating voltages are well below 3 volts.

In addition, IMEC has also looked into the impact of film crystallinity on the operation of RRAM cells, especially with a view to further scaling. It also sheds light on the role of the cap layer and on the switching mechanisms





3. IEDM: SuVolta transistor operates down to 0.4-V


Peter Clarke 12/7/2011 7:28 AM EST
LONDON – Startup SuVolta Inc. has announced that its novel transistor technology, dubbed PowerShrink, operates down to 0.425-V, approximately 300-mV below conventional processes. PowerShrink is based on a deeply depleted channel (DDC) transistor manufactured in epitixially grown doped silicon on the surface of a conventional bulk CMOS wafer.

The progress is set to be discussed in a paper due to be presented at the International Electron Device Meeting presented by a researcher from Fujitsu Semiconductor Ltd.

The paper entitled: Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications, is co-authored by Fujitsu and SuVolta (Los Gatos, Calif.).

The reduction in variation is important because leakage current in transistors is exponentially dependent on VT and power dissipation is dominated by the low edge of the VT distribution. The tighter the distribution the lower the VT can be set.

Fujitsu has demonstrated low voltage operation of a 576-kbit SRAM block based on SuVolta's PowerShrink implemented in a 65-nm CMOS process technology. SuVolta is pitching PowerShrink as an alternative to both FinFETs and fully depleted SOI (FDSOI) which are generally considered to be the major strands of process technology beyond 22-nm. Intel has already introduced a FinFET process technology.

SuVolta's is hoping that publicly disclosed progress by Fujitsu will help persuade process research groups that its approach is superior to FinFET in that it more easily supports multiple threshold voltages over a wider voltage range, and lower cost than FDSOI in that it does not require premium-priced SOI wafers as its starting point

Jeff Lewis, senior vice president of marketing and business development, confirmed that SuVolta is engaged with multiple foundries working on 28-nm and expected results at that process node to emerge in 2012.

The DDC technology matches well with existing infrastructures including existing system-on-chip (SoC) design layouts, existing design schemes such as body bias control, and existing manufacturing tools, said Lewis.

SuVolta argues that one reason that the scaling of supply voltage stopped at the 130-nm node was because of random dopant fluctuation (RDF) in the implanted dopants in the transistor channel. RDF results in variation in threshold voltage (VT) between different transistors on a chip.

Successful reduction of RDF has been reported using two exotic structures, ETSOI and Tri-Gate – a FinFET technology. However, both ETSOI and FinFET technologies are complex, making them difficult to match with existing design and manufacturing infrastructures.

DDC achieves tight control of dopants in layers of epitaxial silicon growth to define a thin channel at the start of the manufacturing process. Thereafter the process is a conventional bulk CMOS process but without the need to inject dopants using ion implantation. According to the Fujitsu paper intra-die VT variation is reduced by half through the use of DDC compared with Fujitsu's non-DDC 65-nm CMOS.

The DDC (deeply depleted channel) transistor shows tight control of dopant concentration and depletion depth. It improves VT matching and is additive to ten years of developments in strain engineering. The no-, low- and high-dopant concentrations are achieved through multiple growth phases of epitaxial silicon prior to device fabrication. The regions are not shown to scale. Source: SuVolta.

The cross sectional transmission electron micrograph (TEM) shows the transistor fabricated on a planar bulk silicon structure. Source: SuVolta





4.IBM, Micron to build hybrid memory with TSVs



12/1/2011 12:11 PM ESTSAN FRANCISCO—

Micron Technology Inc's hybrid memory cube (HMC) will become the first commercial CMOS manufacturing technology to employee IBM Corp.'s through-silicon via (TSV) process, the companies said Thursday (Dec. 1).

According to IBM (Armonk, N.Y.), the TSVs will enable Micron's HMC devices to achieve speeds 15 times faster than current technology. HMC parts will be manufactured at IBM's advanced semiconductor fab in East Fishkill, N.Y., using the company's 32-nm, high-K metal gate process technology, the companies said.

In October, Micron and South Korea's Samsung Electronics Co. Ltd. announced the formation of an open consortium around HMC, a technology that brings DRAM memory and logic processes together into one package to offer potential power efficiency, bandwidth, density and scalability advantages over traditional DRAM. HMC technology uses advanced TSVs—vertical conduits that electrically connect a stack of individual chips—to combine high-performance logic with Micron's DRAM, the companies said.

IBM said it would the details of its TSV manufacturing breakthrough at the IEEE International Electron Devices Meeting on Dec. 5 in Washington, D.C.