LONDON – Startup SuVolta Inc. has announced that its novel transistor technology, dubbed PowerShrink, operates down to 0.425-V, approximately 300-mV below conventional processes. PowerShrink is based on a deeply depleted channel (DDC) transistor manufactured in epitixially grown doped silicon on the surface of a conventional bulk CMOS wafer.
The progress is set to be discussed in a paper due to be presented at the International Electron Device Meeting presented by a researcher from Fujitsu Semiconductor Ltd.
The paper entitled: Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications, is co-authored by Fujitsu and SuVolta (Los Gatos, Calif.).
The reduction in variation is important because leakage current in transistors is exponentially dependent on VT and power dissipation is dominated by the low edge of the VT distribution. The tighter the distribution the lower the VT can be set.
Fujitsu has demonstrated low voltage operation of a 576-kbit SRAM block based on SuVolta's PowerShrink implemented in a 65-nm CMOS process technology. SuVolta is pitching PowerShrink as an alternative to both FinFETs and fully depleted SOI (FDSOI) which are generally considered to be the major strands of process technology beyond 22-nm. Intel has already introduced a FinFET process technology.
SuVolta's is hoping that publicly disclosed progress by Fujitsu will help persuade process research groups that its approach is superior to FinFET in that it more easily supports multiple threshold voltages over a wider voltage range, and lower cost than FDSOI in that it does not require premium-priced SOI wafers as its starting point
Jeff Lewis, senior vice president of marketing and business development, confirmed that SuVolta is engaged with multiple foundries working on 28-nm and expected results at that process node to emerge in 2012.
The DDC technology matches well with existing infrastructures including existing system-on-chip (SoC) design layouts, existing design schemes such as body bias control, and existing manufacturing tools, said Lewis.
SuVolta argues that one reason that the scaling of supply voltage stopped at the 130-nm node was because of random dopant fluctuation (RDF) in the implanted dopants in the transistor channel. RDF results in variation in threshold voltage (VT) between different transistors on a chip.
Successful reduction of RDF has been reported using two exotic structures, ETSOI and Tri-Gate – a FinFET technology. However, both ETSOI and FinFET technologies are complex, making them difficult to match with existing design and manufacturing infrastructures.
DDC achieves tight control of dopants in layers of epitaxial silicon growth to define a thin channel at the start of the manufacturing process. Thereafter the process is a conventional bulk CMOS process but without the need to inject dopants using ion implantation. According to the Fujitsu paper intra-die VT variation is reduced by half through the use of DDC compared with Fujitsu's non-DDC 65-nm CMOS.
The DDC (deeply depleted channel) transistor shows tight control of dopant concentration and depletion depth. It improves VT matching and is additive to ten years of developments in strain engineering. The no-, low- and high-dopant concentrations are achieved through multiple growth phases of epitaxial silicon prior to device fabrication. The regions are not shown to scale. Source: SuVolta.
The cross sectional transmission electron micrograph (TEM) shows the transistor fabricated on a planar bulk silicon structure. Source: SuVolta