NEC, Sony, Toshiba outline 45-nm process advance

Solid State Technology Online Article Ron@Maltiel-consulting.com - Semiconductor & Patent Expert Consulting

Litigation expert consultant and patent expert witness for process, device, and circuit of Dynamic

Ram (DRAM), Flash (NAND, NOR, EEPROM), and Static Ram (SRAM) Memories,

and Microprocessor, Logic, and Analog Devices

News from IEDM: Toshiba, Sony, NEC tip details of 45nm LSI

http://sst.pennnet.com/display_article/280081/5/ARTCL/none/TECHN/News-from-IEDM:-Toshiba,-Sony,-NEC-tip-details-of-45nm-LSI

December 15, 2006 - Toshiba Corp., Sony Corp., and NEC Electronics Corp. unveiled details about their codevelopment of an LSI mass-production platform for 45nm process technology, including use of a fully renovated MOSFET integration scheme, and hybrid structure with low-k film.

The MOSFET integration process applies strained silicon technology utilizing crystal lattice distortion to induce performance-boosting local strain at key locations. Forming stress film on the source/drain integration as well as the upper part of the transistors enhances the strain effect, resulting in 30% faster transistor performance than current process technology as a whole, the companies said, and an improvement in transistor drive current of >20% and >60% in the nMOS and pMOS transistor modes, respectively (see table).

Application of strained silicon technology and performance improvement

Upper transistor part Source and drain part Improvement against current drive performance Drive current

nMOS High stress tensile liner Stress memorization technique >20% 1100µA/µm (Ion)/100nA/µm (Ioff)
pMOS High compressive liner Embedded silicon germanium (eSiGe) >60% 700µA/µm (Ion)/100nA/µm (Ioff)

In the backend process, the partners formed a LSI interconnect layer with a hybrid dual-damascene structure, applying an optimized porous low-k films (with an effective 15-year lifetime, surpassing the average lifetime of a high performance LSI) to both the interconnect layer and the via layer to reduce parasitic capacitance between the interconnect layers. Optimizing the manufacturing process achieved a 45nm-process-suitable effective dielectric constant (k_eff=2.7), and tests show layer yields >98%, matching those of actual production, the companies said, in a statement.

The three partners also described their use of ultrahigh-NA (>1.0) immersion lithography, which they used to create contact holes to the expected size on an ultrahigh-density SRAM, meeting demand tolerances for LSI internal structures -- and confirming sufficient accuracy to apply immersion litho to every circuit, the companies said. (See image below: "Contact holes on an UHD-SRAM processed with dry lithography vary widely (left), whereas there are few variations with ultra high NA immersion lithography.")

Ron@Maltiel-consulting.com - Semiconductor & Patent Expert Consulting

Litigation expert consultant and patent expert witness for process, device, and circuit of Dynamic

Ram (DRAM), Flash (NAND, NOR, EEPROM), and Static Ram (SRAM) Memories,

and Microprocessor, Logic, and Analog Devices

EE Times: Semi News
NEC, Sony, Toshiba outline 45-nm process advance

John Walko (12/14/2006 8:00 AM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=196604112

LONDON — The three Japanese companies that are working together to develop logic process technologies for the 45-nm generation — NEC Electronics Corporation, Toshiba Corporation and Sony Corporation — said they have moved closer to their target with the development of an LSI mass production platform.

The group said Thursday (Dec. 14) the platform integrates "elemental breakthroughs" that "optimize a balance of high performance and high reliability while combining individual elemental technology with new technologies and improvements."

The announcement was made at this week's International Electron Devices Meeting (IEDM) in San Francisco.

The key elements of the platform are a fully renovated Mosfet integration scheme, and a hybrid structure with a low dielectric constant (low-k) film that assures high performance and reliability.

The Mosfet integration process is said to apply strained silicon technology to the transistor, utilizing crystal lattice distortion to induce performance-boosting local strain at key locations. The researchers suggested in their paper at the conference that optimization of the strain boosts transistor performance to a level 30 percent faster than that achieved in the present generation of technology.

They said application of a low-k film in the intermediate metal layer of the chip during the back-end process reduces parasitic capacitance and improves circuit performance.

In the back-end process, the LSI interconnect layer is formed with a hybrid dual-damascene structure, with optimized porous low-k films applied to both the interconnect layer and the via layer. The researchers said this approach enhances control of the interconnect profile.

The partners confirmed a dielectric gate film with an effective 15-year lifetime, a span surpassing the average lifetime of a high performance LSI. They also carried out exhaustive tests of the platform and proved a layer yield of over 98 percent for the back-end process, confirming that the technology achieves the reliability essential for mass production.

The researchers used immersion lithography technology with a numerical aperture (NA) of over 1.0 to make the transistor node, achieving a cell with an area of 0.248 square microns in a very high density SRAM. The cell is said to be the smallest yet achieved.

The three companies are simultaneously developing two 45-nm processes -- the current platform, which is ideal for high performance LSIs, as well as a platform for applications with low power consumption requirements, which is expected to be completed in early 2007.