The highly competitive NAND flash market just got tighter, with the introduction of IM Flash Technologies' newest device, a 50-nanometer, 4-Gbit offering. This announcement comes as a surprise to the industry, since production in the 55-nm or 50-nm nodes was not anticipated until late 2006 or early 2007. In getting this device into the market, IM Flash Technologies has leapfrogged leading flash vendors Toshiba and Samsung in process technology. And it has gained an advantage in the NAND flash sector that is invaluable in this cost-sensitive marketplace.

The flash market

IM Flash Technologies (IMFT) is the latest company to enter the NAND flash market. The company, which was formed earlier this year by Micron Technology Inc. and Intel Corp., combines Intel's expertise with NOR multilevel cell (MLC) flash and Micron's knowledge of DRAM and NAND flash. Micron's first NAND flash offering was a 2-Gbit single-level-cell (SLC) device manufactured at the 90-nm process node. At the time of its release, Micron's offering lagged earlier introductions of 2-Gbit devices from Samsung and Toshiba. Despite that disadvantage, however, it managed to remain competitive with those devices, and, thus, was a commendable first offering. Micron, however, and later IM Flash Technologies, would need to close the gap between their products and leading-edge NAND flash devices.

Micron has extensive experience in commodity memory markets and is one of the top DRAM manufacturers. The company was ranked third in 2005 revenue by iSuppli. Micron's strategy in the highly competitive DRAM marketplace has always been to be an innovative cost reducer, however. So instead of becoming a manufacturer that aggressively pushed its technology into advanced geometries like Samsung, it became a manufacturer that moved into a new process node and focused its innovative efforts on reducing costs to give it a competitive advantage.

An example of that innovation is Micron's move to 6F² DRAM cell sizes from 8F² cell sizes before any other DRAM producer managed to make that move. Semiconductor Insights (SI) analyzed the first 6F² devices in 2004: 130-nm devices from Micron. In 2006, Micron also released a 95-nm 6F² device while Samsung offered a 110-nm solution.

On another front, SI recently examined the patent landscape in the NAND flash market and found that Samsung and Toshiba held the top two positions. This analysis did not include patent applications, however. Although Micron is the third-ranked vendor, SI believes that Micron/IM Flash Technologies will be a more prominent member of this patent landscape once its patents complete the application process. And patent authorities recognize Micron as an innovator. SI believes that Micron's innovations have historically consisted of work in the areas of DRAMs and image sensors, but in recent years this also has likely included NAND flash development.

Intel, on the other hand, has enjoyed success in the NOR flash market by being at the forefront of the industry and cost-reducing its devices through its MLC technology or Intel StrataFlash memory devices. Although Spansion has threatened this position in recent years, Intel is successfully responding by rapidly moving its technology into the 65-nm node to extend its leadership position.

Intel is now also developing its sixth generation of products. The company's experience is valuable, because it provides industry-leading flash manufacturing and MLC knowledge to the IMFT partnership. Intel is also an expert in pushing its processors into advanced process nodes using its ETOX technology. And although NAND flash processes are quite different from those logic processes, the rapid development of 50-nm technology proves that useful knowledge transfer is occurring.

The release of a 50-nm IMFT NAND flash signals that NAND flash development at the joint venture will not strictly follow the strategies traditionally used by either of its parents. The most notable change resides with Micron, as its strategy changes from an effective cost innovator to a front-running innovator. Both Intel and Micron's innovative efforts will now be focused on driving their NAND technology into advanced process nodes.

The NAND flash market is a very competitive environment, with all of the major players moving aggressively to new process nodes. By moving quickly to advanced process technologies, IMFT will be able to manufacture its devices with smaller die sizes. The small die sizes translate into more dies per wafer and, thus, lower manufacturing costs, ultimately allowing more price flexibility.

If it is able to maintain this technology leadership, this strategy will give IM Flash Technologies a competitive advantage in the memory industry.

In addition to the advantages provided by moving quickly to advanced process nodes, IMFT may also be able to dynamically adjust fab capacity between NAND and DRAM devices to meet demand. Some NAND flash manufacturers, like Samsung and Hynix, can adjust capacity as well, but Toshiba does not have a significant presence in the DRAM market and does not share that advantage. Toshiba mitigates this disadvantage, however, by offering foundry services to other organizations.

The MT29F4G08AABWP/JS29F04G08 AANC is a 4-Gbit SLC NAND flash manufactured in a three-metal, triple-poly 50-nm CMOS process. It is the most advanced device currently available in the flash market and marks a significant leap forward for IMFT. In moving to the 50-nm node, the company addressed technology and manufacturing issues associated with NAND manufacturing at advanced geometries.

Inside the 4-Gbit SLC
The 4-Gbit device measures 8 x 12.2 mm for a total die area of approximately 98 mm². In comparison with Micron's 90-nm 2-Gbit device, this represents a 34.7 percent reduction in die size, while the density is doubled. The device's layout is similar to other 4-Gbit parts. The memory arrays are placed in the top portion of the device, and control and peripheral circuitry is found on the bottom of the die. This appears to be the standard design format for the 4-Gbit generation.

The single-transistor NAND flash cell measures 100 x 100 nm for a total area of 0.01 µm². The technology generation is 50 nm, as determined by the poly 2 world line half-pitch in the memory array. Minimum gate length in the array is 55 nm at the bottom of poly 1 floating gate. The cell size is in line with NAND flash 4F² cell sizes. The 4F² cell factor for NAND flash is the smallest cell factor of any memory technology and is the main reason NAND devices have such a low cost-per-bit rating. The effective cell size for the device is 0.0138 µm². The cell size for the device demonstrates a significant advantage over any other flash memories seen to date and allows IMFT to achieve a very effective die size. IMFT also implemented some novel techniques in cell and contact spacing that SI has not observed in any other NAND flash. These techniques likely assisted lithography tools and enhanced reliability.

The 50-nm process uses dual shallow-trench isolation (STI) triple-gate oxide, along with oxide sidewall spacers. The STI configuration in the array is unique and consists of different isolation dimensions. SI believes that the novel configuration was implemented to reduce local stresses and decrease leakage currents. Other array innovations include a novel source line structure while the metal levels on the device are a combination of tungsten and aluminum.

The device uses SLC technology or stores only one bit per memory cell. SLC technology has been the standard flash technology for many years and is easier to implement than MLC technologies. SLC technology is more reliable than MLC devices and requires less testing time, but suffers a cost disadvantage compared with MLC implementations. Because IMFT was pushing processing limits when it jumped to the 50-nm node, SLC was a better option, since it simplified the transition as much as possible.

The 4-Gbit generation
IMFT's newest device now has the smallest die size and thus the lowest cost of any of the 4-Gbit parts examined by SI to date. Since 55- or 50-nm process geometries were not anticipated to hit the market until late 2006 or early 2007, IMFT's device represents a significant accomplishment. As it moves ahead of NAND incumbents Toshiba and Samsung in process technology, it is changing the competitive landscape in that market segment.

The 4-Gbit NAND flash generation is becoming an extremely competitive area, with several vendors offering similar devices. The IMFT device is 25 percent smaller than the next smallest 4-Gbit offering from Samsung, which is manufactured at the 65-nm node--the second most-advanced process currently available.

Die size has a direct effect on the manufacturing costs for NAND flash devices. Calculations show that IMFT can manufacture 160 more gross die per wafer, or 34 percent more die per wafer, than the 65-nm device. These advantages will be sure to lower the company's cost structure.

The IMFT 50-nm offering is a SLC device and offers a higher degree of reliability than MLC technology, despite the lower cost of MLCs. Currently all of the 4-Gbit MLC devices that SI has examined are manufactured in the 90-nm node, and it's believed that manufacturers are transitioning the technology to the 65- and 70-nm process nodes. Even as MLC devices transition to those geometries, they will likely have comparable die sizes to IMFT's part.

IMFT is likely to face significant pressure from the other NAND flash players as they move quickly to equalize any competitive advantage that IMFT now holds. Samsung's historical strategy has been to move quickly to new geometries, and it will not sit idly by with IMFT now at the 50-nm node.

A different ballgame
Toshiba, on the other hand, represents a different type of competition. It traditionally uses MLC technology to optimize densities. Even with its 50-nm technology, IMFT still does not match Toshiba's 56.5-Mbit/mm² rating on its 8-Gbit, 70-nm MLC device.

Toshiba's ability to utilize MLC technology currently gives it an advantage over its competitors. Samsung is moving toward the MLC strategy as well and plans to introduce MLC devices ahead of SLC devices in future generations. Other manufacturers, including IMFT, are stepping up their MLC efforts.

While all manufacturers now have MLC devices, Toshiba is the only one with 70-nm MLC technology that SI has examined. Therefore, expect more MLC devices at advanced geometries in the near future from IMFT and its competitors.

The upcoming arrival of Intel's Robson technology and the implementation of SLC technology will affect the NAND flash landscape as well. Demonstrations of Robson, solid-state drive and hybrid hard-drive technology at the recent Flash Memory Summit show that the technology offers significant advantages over existing architectures. Reliability concerns over MLC NAND flash likely mean that the initial NAND flash devices used in either the Robson or hybrid drive technology will be SLC NAND. The IMFT offering is therefore ideally suited to meet these initial requirements: A single 8-Gbit chip can provide 512 Mbytes of NAND flash buffering.

Fully managed NAND flash solutions also could affect the use of NAND flash, since they will combine wear leveling, ECC and file management into one solution. This will allow OEMs to integrate NAND flash into embedded systems--a task that is difficult with raw NAND flash. Micron's Managed NAND, Sandisk's iNAND and M-Systems' mDOC H3 solutions offer managed solutions, and this gives an advantage to any manufacturer with expertise in flash management. Full control of flash management will also allow those manufactures to compensate for any weaknesses they may have in technology, especially with MLC devices. Therefore, if those interfaces gain market acceptance, demand for MLCflash will increase.

Regardless of where the flash market will go, IMFT is now extremely well-positioned because it has successfully moved its flash technology to the 50-nm node.

In the process of moving ahead, the company addressed several scaling challenges, including cell alignment, tunnel oxide thickness and flash cell coupling. With a 50-nm offering that has put the company on par with the leaders in NAND flash, it can now turn its attention to sub-50-nm technology nodes and MLC technology development.

Now that IMFT has addressed those issues at the 50-nm node, SI expects the company to expand its product line with an MLC device and focus on further process advancement. Indeed, IMFT will need to develop an MLC product in order to compete with other MLC devices for design slots in cost-sensitive applications.

IM Flash Technologies now has a process advantage in the NAND flash market that it will need to continue to aggressively investigate and implement in order to retain its process leadership.

By Geoff MacGillivray, lead technology analyst for memory at Semiconductor Insights (Kanata, Ontario)

  Other 2-Gibit devices at time of Micron's release (2005)

  NAND flash patent review

  Comparison of 4-Gbit NAND flash devices