- Semiconductor & Patent Expert Consulting

RMG and Associates

Providing Silicon Valley Semiconductor Consulting

(408) 446-3040



ISSCC 2009 Preview


1. 3D buzz centers on through-silicon vias/ EETimes

2. Intel says 32 nm on track for late 2009 / EETimes

3. Samsung shows 8 Gbit DRAM at ISSCC/ EETimes

4. ISSCC points to tomorrow's cellphone / EETimes



1. 3D buzz centers on through-silicon vias

BURLINGAME, Calif. -- Chip scaling is showing no signs of hitting the wall--yet. But one alternative path--3D technology based on through-silicon vias (TSVs)--continues to generate steam.

In fact, TSV technology took center stage at the IEEE 2008 International Interconnect Technology Conference (IITC) here this week. Georgia Institute of Technology, IBM, IMEC, Fraunhofer, Tohoku University, TSMC and others presented papers on TSV at IITC, although there is still no consensus just how the industry will bring the long-awaited technology into the mainstream.

Is TSV all hype or a reality? The industry has been talking about TSV technology for years, but there are few products to show for it. One of the few TSV-based products in the market is a CMOS image sensor from Toshiba Corp. Other TSV devices are being demonstrated by IBM and the large memory houses.

There are a range of complex and competing technologies in the arena, many of which are unproven and costly. On the manufacturing front, there are a handful of proposals: chip-to-wafer, wafer-to-wafer, TSV first, TSV last and even self assembly. There are also a number of competing material schemes: copper-to-copper, gold-to-gold, solder and others.

Each methodology, which has various trade-offs, could eventually find a place in the commercial market, said Michael Shapiro, senior technical staff member in the Systems and Technology Group at IBM Corp. "It may be application specific," Shapiro told EE Times at IITC. "It depends on what you're going to do."

The question is whether TSV-based technology will enter the mainstream or remain a niche. "I think it's a going to be mainstream," he said.

"We're already seeing it in CMOS image sensors," said Dean Freeman, an analyst with Gartner Inc. "The memory guys are looking very hard at it."

Chip scaling will continue for some time, but the costs are becoming enormous. So, some chip makers are looking at devising 3D devices using ICs with current-generation geometries. The devices are then connected using tiny and multiple TSVs.

The need for 3-D interconnects and packages has become more critical amid what some call a looming interconnect crisis experts believe could emerge by 2009. The crisis stems from the fact that chip scaling is shrinking the aluminum or copper interconnects in chip designs, causing potential timing delays and unwanted copper resistance.

TSV technology remains immature and expensive. Heat dissipation in the silicon stacks is a major problem. A few companies are sampling TSV products, but none have shown the potential to replace today's entrenched wire-bonding techniques or new advances in package-on-package technology.

"Electromigration is a well-known root cause for reliability problems" in 3D integration, said Riet Labie, a researcher at IMEC, a Belgium-based R&D group.

IBM, Intel, Elpida, Samsung, Toshiba and a growing list of companies have talked about or demonstrated devices based on TSV technology. The list continues to grow, as a number of entities at IITC presented ways to propel the technology into the mainstream.

For example, silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) claims to have developed a production process in the arena. In a paper at IITC, entitled "Production Worthy 3D Interconnect Technology," TSMC proposes a method that would fabricate the vias in the fab or in the front-end-of-the-line (FEOL).

The so-called ''via first'' approach is somewhat competitive to proposals, which would fabricate the vias in the backend or in an IC-packaging house.

TSMC also proposes to fabricate the vias with two methods: wafer-to-wafer and die-on-wafer. Each method would use a copper-to-copper thermo-compression metallization scheme to bond the wafer to the wafer or the die to the wafer.

TSMC's TSVs, which were filled with both copper and tungsten interconnect materials, are said to have high-aspect ratios of 8:1 and 15:1.

Others are taking a different approach to the technology, but all agreed there are some major issues with TSVs. "Everyone talks about cost and reliability," said Armin Klumpp, a physicist with the Fraunhofer Institute for Reliability and Microintegration.

At IITC, Fraunhofer described the latest findings within a European project, dubbed "Through-Silicon Via Technologies for Extreme Miniaturized 3D Integrated Wireless Sensor Systems.''

The three-year project, also called e-Cubes, proposes to devise a tiny wireless sensor node. The projected started in 2006. A demonstration product is due out by 2009. The project includes CEA, Infineon, Alcatel, Honeywell, Philips, SensoNor, IMEC and others.

Fraunhofer also described the development of a tire pressure monitor, based on a TSV scheme. To devise this product, Fraunhofer described a technology called ICV-SLID (solid-liquid-interdiffusion) soldering.

The R&D group uses a chip-to-wafer bonding method. A 3D chip has been fabricated by bonding the chip on the wafer with 10-um thin soldering pads. The TSVs were processed in the front-end via a copper/tin metal system. In one experiment, the group claims to have devised 2 x 10-micron2 and 20-micron deep TSVs.

A more exotic approach is being taken Tohoku University, which proposes a 3D technology based on a chip-to-wafer bonding technique, dubbed ''super-chip'' integration.

''After wafer probing and dicing many known good dies (KGDs) with TSVs for the first layer of 3D, LSIs are simultaneously aligned using a self-assembly technique and bonded to the chips on a LSI wafer through the metal micro-bumps,'' according to a paper from the university.

The self assembly process is done by growing silicon dioxide films on a wafer. Then, so-called hydrophilic areas are patterned on a wafer via lithography. Then, aqueous solutions are dropped on the hydrophilic areas. The silicon films are then aligned on the wafer via a self-assembly process, said Mitsu Koyangai, a professor at Tohoku University, at IITC.

Silicon chips with sizes of 1-mm2 to 5-mm2 square are assembled with alignment accuracy of less than 0.5-micron, he said at the event.

TSVs are a hot topic, but this is not the only way to achieve 3D. Besides its efforts in e-Cubes, IMEC is looking at another technology: micro-bump interconnects for 3D-device stacking.

To accomplish this 3D technology, IMEC uses chip-to-chip interconnections and flip-chip solder bonding. Solder-based intermetallic bonding is used as an alternative to standard solder flip-chip interconnections.

In one experiment at IMEC, chips are bonded with a 48 x 48 area array of intermetallic interconnections. Two separate metal joint types can be used: copper-to-tin and cobalt-to-tin.

In this process, single bump structures are fabricated on the chip. Routing lines are then produced using a wafer-level packaging redistribution process that is said to yield 5-micron thick copper lines.




2. Intel says 32 nm on track for late 2009

Intel says 32 nm on track for late 2009
CPU giant presenting 15 papers at ISSCC
SAN JOSE, Calif. — Despite recent layoffs and fab closings, Intel Corp. remains on track to deliver its first 32nm processors before the end of the year. The update came as part of a conference call previewing some of the papers the processor giant will present at next week's International Solid-State Circuits Conference (ISSCC).

"The 32 nm technology is getting ready to go into the manufacturing phase, we are lining up fabs to support it and we expect great demand," said Mark Bohr, director of Intel's technology and manufacturing group. "We are on track for shipping products in the fourth quarter and have 22 nm technology in development for 2011," he said.

Intel will present 15 papers at ISSCC including four of eight at a session on microprocessors where it will describe its latest 45 nm Nehalem and Itanium chips. None of its rivals--Advanced Micro Devices, IBM or Sparc partners Fujitsu and Sun Microsystems—will present on their CPUs.

Bohr will give a keynote talk at ISSCC on the coming era of system-on-chip devices, using the integration in its latest Nehalem and mobile Atom processors as examples. "Modern microprocessors are truly digital SoCs because they include high performance logic, memory and analog circuits," Bohr said.

The company is actually something of a latecomer to SoCs. It launched a major initiative in the area in 2007 and debuted one of its first full blown SoCs, the Canmore TV chip, just last year.

Beyond its work in processors, Intel will present at ISSCC a wide range of papers.

For example, it will describe a 2.5 GSample/second analog-digital converter with 7-bit precision built from an array of simple ADC elements. It will also discuss a single instruction, multiple data accelerator that can run on as little as 230 millivolts.

"This will help us deliver better graphics on battery-powered systems," said Krishnamurthy Soumyanath, director of communications circuit research at Intel.



3.Samsung shows 8 Gbit DRAM at ISSCC

Die stacking enables dense memories, imagers, SoCs
SAN JOSE, Calif. — Samsung will describe 4 and 8 Gbit DRAM chips, and a team from Toshiba and SanDisk will detail a 64 Gbit NAND flash chip packing four bits per cell at the International Solid State Circuits Conference in February. The 8 Gbit DRAM is one of many chips to be described at the event using vertical stacking techniques.

Also at ISSCC, Intel will describe an eight-core x86 server chip using a whopping 2.3 billion transistors. Intel will dominate the session on microprocessors with four of eight papers, none from rivals such as Advanced Micro Devices, IBM or Sparc partners Fujitsu and Sun Microsystems. . Samsung will detail a design that stacks four 2 Gbit DDR3 DRAMs using through silicon vias. The paper will describe new check and repair techniques for the vias that boost yield by 15 to 98 percent.

The stacking technique is increasingly seen as a key tool for tomorrow's system-in-package devices. In a separate paper, Toshiba will describe its use of through silicon vias to create a CMOS imager module that significantly reduces the size and cost compared to existing chips.

A team from Irvine Sensors, Forza Silicon and MIT Lincoln Lab will present a paper on a Mpixel CMOS sensor that includes a stack of 2x32-channel analog digital converters. The use of such stacking techniques in imagers should being lower cost, high performance cameras to mobile devices, said ISSCC organizers.

Separately, NEC will describe a novel approach to 3-D chip stacking that links an SRAM and system-on-chip dice by electrodes with a 10 micron pitch. The approach replaces micro-bumps with 50 micron pitches.

On the memory front, a team of researchers from Toshiba and SanDisk will describe a 64 Gbit NAND flash chip that packs four-bits per cell using a technique that creates 16 distinct storage levels. The chip is made in a 43nm process and can write at speeds up to 5.6 Mbits/second using a three-step programming method.

"Achieving 16 levels of discrimination in a flash cell is a very analog problem that's pretty interesting," said Ken Smith, one of the ISSCC organizers.

For its part, Samsung will also describe a 4 Gbit DDR3 DRAM running at 1.2 V. It is made in a 56 nm process and supports throughput up to 1.6 Gbits/s/pin.

Intel will kick off a session on microprocessors that includes three papers on its recently announced Nehalem family of CPUs and one on the clocking scheme for a quad-core Itanium processor. At 2.3 billion transistors, the eight-core Nehalem processor is the most dense chip described at ISSCC to date. Intel has said it will ship in late 2009.

Intel authored a number of papers at the event including one that will give a peak into its 32 nm process technology. That paper will detail a 291 Mbit SRAM chip that runs at up to 4 GHz at 1V, made in Intel's 32nm high-K metal gate process.

Another Intel paper will describe the optical interconnects used on its Tera-Scale Computing R&D chip that debuted at last year's event. Nudging closer to terahertz devices, a team from NXP Semiconductors, Texas Instruments and the University of Florida will report at ISSCC 2009 on work designing an 800 GHz CMOS phase-locked loop, a building block for future Terahertz-class systems.



4.ISSCC points to tomorrow's cellphone

High def video, 32 Gbits flash and more on tap for mobile
SAN JOSE, Calif. — Imagine a future cellphone with 32 Gbits of flash capable of playing high def video and ranging across networks from the oldest GSM to the latest 3G. That's just one of many future concepts enabled by chip designs that will be described at International Solid State Circuits Conference in February.

Renesas Technology will describe at ISSCC a mobile application processor that can decode 30 frames/second of H.264 video at 1080-progressive resolution while consuming just 342 milliwatts. The 65nm chip fits into a 6.4x6.5 mm package and runs at up to 500 MHz.

Panasonic will detail an even bigger step in low power media with an intermittent operating technique that reduces power consumption for audio playback to just 9.6 mW on its 45 nm application and baseband processors.

Toshiba and SanDisk engineers will describe a 32 Gbit NAND flash chip to meet the memory needs of such handsets. The 113mm2 device fits into a microSD card. It packs three bits per cell and is made in a sub-35 nm process.

In wireless chips, Qualcomm will detail a sing RF CMOS transceiver that can handle services ranging from GSM to UMTS bands 1 to 6 and 8 to 10. The transceiver can also handle global positioning system functions.

In imagers, Canon will discuss a 3.3 Mpixel CMOS sensor that uses new column readout circuits to lower noise by 30 percent. The chip promises higher quality video and imaging for mobile devices.

Finally, researchers from Elmos Semiconductor and the Helsinki University of Technology will detail a new interface to a micro-gyroscope. The design reduces the size of the interface to 2.5mm2 in a 35 nm process and cuts the sensor startup time to 0.4 seconds.