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BURLINGAME, Calif. -- Chip scaling is showing no signs of hitting the wall--yet. But one alternative path--3D technology based on through-silicon vias (TSVs)--continues to generate steam.
In fact, TSV technology took center stage at the IEEE 2008 International Interconnect Technology Conference (IITC) here this week. Georgia Institute of Technology, IBM, IMEC, Fraunhofer, Tohoku University, TSMC and others presented papers on TSV at IITC, although there is still no consensus just how the industry will bring the long-awaited technology into the mainstream.
Is TSV all hype or a reality? The industry has been talking about TSV technology for years, but there are few products to show for it. One of the few TSV-based products in the market is a CMOS image sensor from Toshiba Corp. Other TSV devices are being demonstrated by IBM and the large memory houses.
There are a range of complex and competing technologies in the arena, many of which are unproven and costly. On the manufacturing front, there are a handful of proposals: chip-to-wafer, wafer-to-wafer, TSV first, TSV last and even self assembly. There are also a number of competing material schemes: copper-to-copper, gold-to-gold, solder and others.
Each methodology, which has various trade-offs, could eventually find a place in the commercial market, said Michael Shapiro, senior technical staff member in the Systems and Technology Group at IBM Corp. "It may be application specific," Shapiro told EE Times at IITC. "It depends on what you're going to do."
The question is whether TSV-based technology will enter the mainstream or remain a niche. "I think it's a going to be mainstream," he said.
"We're already seeing it in CMOS image sensors," said Dean Freeman, an analyst with Gartner Inc. "The memory guys are looking very hard at it."
Chip scaling will continue for some time, but the costs are becoming enormous. So, some chip makers are looking at devising 3D devices using ICs with current-generation geometries. The devices are then connected using tiny and multiple TSVs.
The need for 3-D interconnects and packages has become more critical amid what some call a looming interconnect crisis experts believe could emerge by 2009. The crisis stems from the fact that chip scaling is shrinking the aluminum or copper interconnects in chip designs, causing potential timing delays and unwanted copper resistance.
TSV technology remains immature and expensive. Heat dissipation in the silicon stacks is a major problem. A few companies are sampling TSV products, but none have shown the potential to replace today's entrenched wire-bonding techniques or new advances in package-on-package technology.
"Electromigration is a well-known root cause for reliability problems" in 3D integration, said Riet Labie, a researcher at IMEC, a Belgium-based R&D group.
IBM, Intel, Elpida, Samsung, Toshiba and a growing list of companies have talked about or demonstrated devices based on TSV technology. The list continues to grow, as a number of entities at IITC presented ways to propel the technology into the mainstream.
For example, silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) claims to have developed a production process in the arena. In a paper at IITC, entitled "Production Worthy 3D Interconnect Technology," TSMC proposes a method that would fabricate the vias in the fab or in the front-end-of-the-line (FEOL).
The so-called ''via first'' approach is somewhat competitive to proposals, which would fabricate the vias in the backend or in an IC-packaging house.
TSMC also proposes to fabricate the vias with two methods: wafer-to-wafer and die-on-wafer. Each method would use a copper-to-copper thermo-compression metallization scheme to bond the wafer to the wafer or the die to the wafer.
TSMC's TSVs, which were filled with both copper and tungsten interconnect materials, are said to have high-aspect ratios of 8:1 and 15:1.
Others are taking a different approach to the technology, but all agreed there are some major issues with TSVs. "Everyone talks about cost and reliability," said Armin Klumpp, a physicist with the Fraunhofer Institute for Reliability and Microintegration.
At IITC, Fraunhofer described the latest findings within a European project, dubbed "Through-Silicon Via Technologies for Extreme Miniaturized 3D Integrated Wireless Sensor Systems.''
The three-year project, also called e-Cubes, proposes to devise a tiny wireless sensor node. The projected started in 2006. A demonstration product is due out by 2009. The project includes CEA, Infineon, Alcatel, Honeywell, Philips, SensoNor, IMEC and others.
Fraunhofer also described the development of a tire pressure monitor, based on a TSV scheme. To devise this product, Fraunhofer described a technology called ICV-SLID (solid-liquid-interdiffusion) soldering.
The R&D group uses a chip-to-wafer bonding method. A 3D chip has been fabricated by bonding the chip on the wafer with 10-um thin soldering pads. The TSVs were processed in the front-end via a copper/tin metal system. In one experiment, the group claims to have devised 2 x 10-micron2 and 20-micron deep TSVs.
A more exotic approach is being taken Tohoku University, which proposes a 3D technology based on a chip-to-wafer bonding technique, dubbed ''super-chip'' integration.
''After wafer probing and dicing many known good dies (KGDs) with TSVs for the first layer of 3D, LSIs are simultaneously aligned using a self-assembly technique and bonded to the chips on a LSI wafer through the metal micro-bumps,'' according to a paper from the university.
The self assembly process is done by growing silicon dioxide films on a wafer. Then, so-called hydrophilic areas are patterned on a wafer via lithography. Then, aqueous solutions are dropped on the hydrophilic areas. The silicon films are then aligned on the wafer via a self-assembly process, said Mitsu Koyangai, a professor at Tohoku University, at IITC.
Silicon chips with sizes of 1-mm2 to 5-mm2 square are assembled with alignment accuracy of less than 0.5-micron, he said at the event.
TSVs are a hot topic, but this is not the only way to achieve 3D. Besides its efforts in e-Cubes, IMEC is looking at another technology: micro-bump interconnects for 3D-device stacking.
To accomplish this 3D technology, IMEC uses chip-to-chip interconnections and flip-chip solder bonding. Solder-based intermetallic bonding is used as an alternative to standard solder flip-chip interconnections.
In one experiment at IMEC, chips are bonded with a 48 x 48 area array of intermetallic interconnections. Two separate metal joint types can be used: copper-to-tin and cobalt-to-tin.
In this process, single bump structures are fabricated on the chip. Routing lines are then produced using a wafer-level packaging redistribution process that is said to yield 5-micron thick copper lines. |
