LONDON — Straining rather scaling transistors is the key to the latest 65-nanometer logic process from Intel Corp., as exemplified in the Pentium D 920 dual-core processor, according to Canadian technology and patent analysis consultancy Semiconductor Insights Inc.
In a statement issued Tuesday (Jan. 24) Semiconductor Insights (Ottawa, Ontario) did not discuss what transistor dimensions it found Intel using in its 65-nanometer logic process, but indicated that Intel has concentrated on straining its 65-nm transistors rather than scaling them.
Semiconductor Insights (SI) said it is performing an analysis of Intel’s 65-nm logic process including transmission and scanning electron microscope (TEM and SEM) photographs and chemical analysis to determine dopants.
“Traditional transistor scaling technology follows the convention of smaller is better. However, our TEM and SEM analysis of Intel's 65-nm Pentium D 920 dual-core processor has revealed an innovative and radical shift in Intel's approach that shifts the focus from scaling physical dimensions towards increasing channel strain and enhancing carrier mobilities,” said Don Scansen, process technology manager for SI, in the statement.
“This innovation avoids the leakage and reliability challenges involved with scaling down the gate oxide thickness or with introducing a new class of materials into the dielectric. This is the promise of strain engineering, and it is clear that strain technology is delivering on its promise at Intel,” he added.
The engineering consultancy said Intel has used SRAM layout optimized for density but nonetheless with dimensions relaxed from Intel's published data on their SRAM test chip.
SI said it is also conducting an analysis of silicon-germanium in the source and drain of the p-type field effect transistors to determine the germanium concentration gradient; an analysis of new silicide processing being used by Intel to enable ultrashallow junctions; and a scanning capacitance analysis of ultrashallow junctions.
According to the measurement parameters included in a description of SI’s report the minimum NMOS and PMOS gate lengths are being taken.
Semiconductor Insights prompted discussion in the industry when it claimed in January 2004 that the Emotion Engine + Graphics Synthesizer otherwise known as the EE+GS@90nm used in a Sony games console was made using a 130-nanometer manufacturing process technology, despite plans to implement the combination chip in a 90-nm manufacturing process and a naming convention that implies the use of a 90-nm process.
Sony denied the charge at the time, arguing that the definition of a manufacturing process was complex and that its own CMOS4 process was in-line with other 90-nm process technologies.
