Latest about Interconnection from Ahmet Ceyhan, and Azad Naeemi, Georgia Institute of Technology in Future-fab.com
The research pipeline of the semiconductor industry involves increasingly radical potential solutions to carry technology advancement through dimensional scaling to beyond-conventional CMOS. Many logic devices are under investigation to extend Moore’s Law to beyond the year 2020. These logic devices differ in structure and operating principles, and include various physical quantities that may be used for encoding information, such as charge, electric dipole, magnetic dipole (spin), orbital state, mechanical position, light intensity, etc. However, any device technology that offers advantages in performance, power dissipation or ease in dimensional scaling will have to be complemented with an interconnect technology that offers similar trades to avoid major bottlenecks due to interconnects. Various carbon-based interconnects were shown to have comparable or better performance compared to Cu/low-k in terms of both resistance-capacitance (rc) product and energy-delay-product...
See an earlier article below
Ahmet Ceyhan, Azad Naeemi
Georgia Institute of Technology
The research pipeline of the semiconductor industry involves increasingly radical potential solutions to carry technology advancement through dimensional scaling to beyond-conventional CMOS. Many logic devices are under investigation to extend Moore's Law to beyond the year 2020. These logic devices differ in structure and operating principles, and include various physical quantities that may be used for encoding information, such as charge, electric dipole, magnetic dipole (spin), orbital state, mechanical position, light intensity, etc. However, any device technology that offers advantages in performance, power dissipation or ease in dimensional scaling will have to be complemented with an interconnect technology that offers similar trades to avoid major bottlenecks due to interconnects, which were described in . Various carbon-based interconnects were shown to have comparable or better performance compared to Cu/low-k in terms of both resistance-capacitance (rc) product and energy-delay-product (EDP).
The aim of this article is to investigate the interactions of interconnects with various voltage-controlled, charge-based devices similar to the conventional Si-CMOS transistor, including high-performance and ultra-low-power options. For that purpose, we pair finFETs, MOSFET-like carbon nanotube FETs (CNFETs), homojunction III-V tunnel FETs (TFETs) and sub-threshold CMOS devices with conventional Cu/low-k and emerging interconnect options; and we compare the relative performances at the circuit level. These device and interconnect technology options are illustrated in Figure 1. Since various device technologies offer very different characteristics in terms of the output current, input capacitance, subthreshold swing, etc., the constraints that they put on interconnects and the best interconnect option for each device are different as well.
This difference stems from the fact that the impacts of technology parameters of various interconnect technologies on the speed and energy advantages of a circuit may differ depending on the transistors used. Emerging carbon nanotube (CNT) and graphene nanoribbon (GNR) interconnects are mostly more resistive than Cu/low-k [3,4], but they offer lower capacitances.
Based on the Berkeley Short-channel IGFET Common Gate Model (BSIM-CMG), predictive technology models (PTMs) for finFET devices are developed jointly by the Arizona State University PTM Group and ARM. The development of the model parameters for the BSIM-CMG model is performed using the scaling theory of multi-gate devices, physical models and ITRS projections. Compared to planar bulk CMOS devices, finFET devices have significantly improved short channel effects (SCE) due to better electrostatics, can carry more current and offer improved area efficiency. The channel width is quantized; hence, the number of fins has to be optimized for drive current choices.
CNFET devices are alternative solutions to performance enhancement of transistors in the "atomic dimension limit" beyond 2020. A compact model developed by Deng et al. is calibrated to meet reasonable ON current requirements while controlling the threshold voltage to keep leakage current at a reasonable value; and used for simulating MOSFET-like CNFET gates at the 16 nm technology node to predict the circuit- and system-level properties of CNFET devices. This model includes various non-idealities, such as the quantum confinement effects on both circumferential and axial directions, elastic scattering in the channel region, the resistive source/drain, the Schottky-barrier resistance, the acoustical and phonon scattering in the channel region, the screening effect by the parallel CNTs in CNFETs that contain multiple parallel CNTs under the same gate, and parasitic gate capacitances.
Figure 1. Interconnect Configuration for Conventional Cu/low-k and Emerging Carbon-Based Interconnect Technologies (left) and the Architectures of the Devices That Are Under Investigation (right).
Conduction in a TFET occurs through band-to-band tunneling between the source and the channel barrier. The gate voltage is used to shift the bands in energy and change the probability of tunneling of carriers. Various materials and structures are proposed including homojunction III-V TFETs, heterojunction III-V TFETs and GNR TFETs. TFETs with single-gate, double-gate or gate-all-around (GAA) architectures are also studied. The principle of operation for all these devices is the same, but they differ in parameters such as supply voltage and drive current. We focus on InAs nanowire-based GAA TFET devices; and we use physics-based compact models to calculate reasonably accurate current-voltage characteristics and gate/parasitic capacitances. InAs nanowires are considered due to their direct bandgap that eliminates the necessity for phonon assistance in tunneling. InAs is a promising material for realizing TFETs thanks to its small bandgap and light hole and electron effective masses, which increase the ON current of the TFET device. Both p-type and n-type TFETs are realized by assuming n++-i-p+ and p++-i-n+ structures, respectively, as shown in Figure 1.
The delay and EDP performances of the device-interconnect pairs are calculated assuming a driver connected to a receiver through an interconnect of varied length, considering a typical fan-out of 3. To perform a fair comparison, we assume a CNFET inverter that is 5 times the minimum size as the driver; and the number of fins in a finFET and the number of nanowires in a TFET are calculated such that the total width of the devices is the same as the CNFET. The fin pitch and nanowire pitch are assumed to be equal and as given in  for each technology node.
Figure 2. Speedup and EDP gain advantages offered by various interconnect designs in finFET circuits at the 16nm (top) and 7 nm (bottom) technology nodes.
In finFET circuits, per unit length values of both the interconnect resistance and capacitance have a significant impact on the circuit delay. Therefore, to outperform Cu/low-k interconnects in finFET circuits, either of these parameters must be reduced significantly while avoiding a significant opposite change in the other parameter. Individual SWNT interconnects with 2 nm diameter have much smaller capacitance per unit length compared to copper interconnects, but they are too resistive to be used in high-performance circuits at the 16 nm technology node. On the other hand, bundles of SWNT interconnects have significantly lower resistance per unit length values compared to Cu interconnects at similar capacitance values. Therefore, as illustrated in Figure 2, the best interconnect option for a finFET circuit in terms of circuit delay is SWNTs manufactured in horizontal bundles. Multi-layer GNR interconnects may outperform Cu interconnects if the edges are perfectly smooth, with a probability of electrons backscattering at the edges equal to 0. Even a moderate 20 percent edge-scattering probability significantly degrades GNR performance.
Figure 3. Speedup and EDP gain advantages offered by various interconnect designs in CNFET circuits at the 16 nm technology node.
Figure 4. Speedup and EDP gain advantages offered by various interconnect designs in TFET circuits at the 16 nm technology node.
Even though it is not possible to outperform Cu interconnects in terms of circuit delay with a few parallel SWNT interconnects at the 16 nm technology node due to their high resistance per unit length, it is possible to benefit from their smaller capacitance per unit length compared to Cu interconnects, which translates into a lower power dissipation. As Figure 2 demonstrates, a mono-layer of SWNTs as dense as 250 SWNTs/µm can offer ˜2x better EDP performance than Cu at ˜100 gate pitches. It is important to note that as technology scales, the impact of size effects on Cu interconnect becomes more pronounced. Since the resistance per unit length of an individual SWNT does not change with scaling as long as its diameter is the same, and that of GNRs increase at a slower rate compared to Cu interconnects, more opportunities arise for using these carbon-based interconnect technologies at highly scaled technology nodes. This fact is illustrated in Figure 2, where it can be seen that SWNTs can offer much larger gains in both circuit delay and EDP at the 7 nm technology node. For this to be possible, however, the density of SWNTs must increase significantly, since the minimum interconnect dimensions where tubes have to be placed are much smaller at future technology nodes. Assuming perfectly reliable connections, a density of at least 125 SWNTs/µm is required to have a connection between the driver and the receiver at the 7 nm technology node.
Figure 5. Speedup and EDP gain advantages offered by various interconnect designs in sub-threshold operation at the 16nm technology node.
The conclusions that can be drawn from simulations using CNFETs are very similar to finFET circuits as plotted in Figure 3. Interconnect resistance and capacitance are equally effective in determining the circuit delay, and bundles of SWNTs can offer the best delay performance due to their smaller interconnect resistance per unit length compared to Cu. CNFET devices offer the highest output current among the device types that are considered in this work. As a consequence, CNFETs are affected more severely from the changes in interconnect resistance per unit length.
Table 1. Comparison Table Summarizing the Simulation Results
TFETs have very different interconnect requirements than finFETs and CNFETs. Due to the lower ON current offered by TFETs, the output resistance of TFET devices is much larger than both of these device technologies. As a result, interconnect resistance is not as crucial in TFET circuits as it is in finFET and CNFET circuits. Reducing interconnect capacitance per unit length is more beneficial in reducing the circuit delay in TFET circuits than reducing the interconnect resistance per unit length. Clearly, reduced interconnect capacitance means lower interconnect power dissipation as well. Figure 4 demonstrates that the best circuit delay can be obtained by using a low-density mono-layer of SWNTs because they offer the smallest interconnect capacitance per unit length. However, the diameter of the tubes in the mono-layer has a non-negligible impact on the speedup as shown in Figure 4 due to the different resistance per unit length values. If tubes with a diameter of 2 nm are used, the resistance per unit length can be reduced compared to 1 nm diameter tubes and a better speedup can be achieved. In short, moderately resistive low-capacitance interconnect technology options must be considered for obtaining the best performance in delay in TFET circuits.
Considering planar bulk MOSFET devices at the 16-nm technology node and operating them at 20 percent of the nominal supply voltage value, it is possible to reduce the power dissipation of a circuit significantly. For these circuits operating at sub-threshold voltage values, devices can be assumed highly resistive. Therefore, the resistance associated with interconnects is a secondary concern to the capacitance. Since wire resistance does not have a significant impact on circuit performance, only SWNTs with 1 nm diameter are considered in plotting Figure 5. Note that as the density of tubes is increased, the associated capacitance per unit length increases and the maximum speedup is lowered.
Table 1 quantifies how much interconnect resistance and capacitance per unit length impact circuit performance for various device types at short and long interconnect lengths. Also, the first three best interconnect options that maximize EDP gain at short and long interconnect lengths for each device are tabulated.
About the Authors
Ahmet Ceyhan received his M.S. in electrical and computer engineering from Rutgers University, New Jersey in 2009. He is currently working toward his Ph.D. at Georgia Institute of Technology, Atlanta.
Azad Naeemi received his M.S. and Ph.D. in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, in 2001 and 2003, respectively. He has been an assistant professor with Georgia Tech since 2008.
An eralier article:
Azad Naeemi,1 David J. Maloney,2 Michele Stucchi3
1Georgia Institute of Technology 2Intermolecular Inc. 3imec
Over the past 15 years, copper interconnect integration has matured from a leading–edge, relatively new technology toward a standard materials and process set. Over this period, its scalability has been repeatedly demonstrated through continuous improvement in materials, toolsets, design and layout, and is a testament to the global community of technologists charged with interconnect fabrication. In a diminishing–returns fashion, however, the challenges facing interconnect going forward are increasingly daunting.
A collection of the most pressing challenges documented in the 2012 ITRS Interconnect chapter (yellow representing identified but immature solutions, and red representing challenges with no known manufacturable solutions) is shown in Table 1. Assembling the significant challenges facing the interconnect community in this manner is visually striking, and conveys the urgency that the interconnect world feels as it works to keep pace with the ITRS.
Among the key challenges the table highlights: the need for controllable, uniform and contiguous deposition of barrier metal for metal 1 at thicknesses below 2 nm after 2014; the need to minimize copper erosion from CMP, especially at tight pitch; the requirement to continually drive contact and via resistance to ever–lower values in the face of shrinking geometries and more dominant effects of barrier and other materials; the need for development of dielectrics of decreasing permittivity while maintaining sufficiently strong mechanical properties; and the required development of damage–free clean and etch processes.
Clearly, then, there is no shortage of challenging projects currently available to the OEM, IDM and materials companies participating in semiconductor interconnect–which is good news, since overcoming these red brick walls is critical to staying on the cost reduction curve (Figure 1) that has been so vital to the continued economics that help to drive the semiconductor industry. Furthermore, it seems unlikely that incremental materials, process and equipment improvements, trickling in at rates typical of other traditional, more mature industries, will be sufficient to overcome the technical challenges being faced (although the outward movement of any given brick wall by just one technology node certainly has value). The development of step–change, radical improvements and novel, disruptive technologies might well be what is required for the semiconductor industry to drive onward.
It is hoped that, far from painting a gloomy view of the future for semiconductor interconnect, the appropriate R&D communities are invigorated by the striking image embodied in Table 1. In a sense, the raison d'être of the ITRS is to spur new and creative approaches to seemingly intractable problems. There is plenty of room to participate in solving these problems, for organizations ranging from small startup and venture–funded operations to established multinational corporations. Equally important is the fundamental, curiosity–driven research from the world's institutions of higher learning that is absolutely necessary in underpinning private–sector development. This research leads to the startups that create new materials, tools and processes and, equally importantly, this research produces the university graduates who are so essential to sustainable innovation.
Encouragingly, solutions for many of the challenges referenced in this article would likely be implemented very quickly–thereby providing immediate payback and, it is hoped, suitable reward for disruptive innovation. As an example, as copper lines have been scaled to ever–smaller dimensions from about the 220 nm node in 1998 to the 14 nm node today, the associated copper diffusion barrier has taken an increasing, and currently disproportionate, volume of available conductor space of the very narrow trenches now required. This trend is illustrated in Figure 2. If a suitable, drop–in replacement barrier to copper diffusion that is no more than 1 nm thick were available today, it would instantly be in high demand. Alternatively, the development of a conductor material to replace copper that requires no barrier would also be very attractive to the industry (if not as immediately implementable). Clearly, though, both of these potential pathways are very challenging and require innovation.
For another example, as scaling has continued to the 14 nm node and beyond, new reliability concerns are constantly emerging. Degradation in time–dependent dielectric breakdown (TDDB) is now one of the major concerns threatening early system failures. Processes such as double patterning using litho–etch–litho–etch (LELE) create offsets in wire dimensions and spacings as shown in the left side of Figure 3. These offsets add to the existing local spacing variations induced by line–edge roughness (LER), thus further raising the electric field in the dielectric material between adjacent wires. In a similar manner, the slightest via misalignment in narrowly spaced interconnects (Figure 3, right), even if permitted by current design rules, locally increases the electric field up to 2 MV/cm2 for advanced low–k materials. These effects will obviously lead to premature TDDB failures.
Interconnect in the Post–CMOS Era
As the electronics industry now looks realistically toward the post–CMOS era, interconnects will continue to be an ever–growing challenge. As always, the introduction of new materials must be validated by breakthrough performance improvements that will justify the concomitant increases in cost and cost–of–ownership for the new tools, materials and processes. A post–CMOS era suggests possible deviations from the current silicon–based infrastructure, which will be costly and potentially difficult to support by the current semiconductor ecosystem without significant performance improvements. For example, Figure 4 shows some possible options for interconnects for devices operating on computational state variables other than electronic charge. Unfortunately, interconnects for most novel state variables are inherently slow. This limitation can be overcome if the interconnect is shortened; however, shorter interconnects can be achieved only if novel devices have smaller footprints or fewer devices are needed for the same set of tasks.
However, the move to non–CMOS–based computing is not imminent. In the meantime, with no clear path forward for novel interconnect introduction, there is a strong need for novel and creative solutions that offer a means to break through some of the red brick walls in Table 1. Any simplification of the current processing complexity through introduction of new tools, processes and materials could push out some of the red brick walls for at least a generation or two.
Tighter design specifications might be required to compensate for more fragile ultralow–k materials, and will no doubt introduce a higher cost and complexity. Finally, the ultimate success of finding new breakthrough interconnect technologies continues to rest with the ecosystem of IDMs, suppliers, startup companies and universities, and the willingness to take creative risks to circumvent the red brick walls in the ITRS.
The authors would like to acknowledge the efforts of the ITRS Interconnect Working Group in making this article possible. A full list of members of the Interconnect Working Group can be found here.
About the Authors
Azad Naeemi is an assistant professor with the School of Electrical and Computer Engineering at the Georgia Institute of Technology. His areas of research include performance modeling for emerging nanoelectronic and spintronic devices and interconnects, and circuit– and system–level implications of emerging technologies.
David J. Maloney
David J. Maloney is an account technology director at Intermolecular, and previously held several technical and management roles during a 15–year career with DuPont. He holds chemistry degrees from McGill University (B.S.) and Texas A&M University (Ph.D.) and an MBA from UC Berkeley's Haas School of Business.
Michele Stucchi is a senior research engineer at imec in Belgium. He received a master's degree in electrical engineering at the University of Bari, Italy. His activities include characterization, modeling and reliability aspects of on–chip interconnects on 2D and 3D stacked ICs.
copyright 2013 Ron Maltiel all rights reserved