New trends in PCBs: Q&A with David Wiens of Mentor Graphics

The downturn of late 2000 to 2002, coupled with high levels of capital investment, placed many PCB companies in a bind. Those that have survived have been the companies best able to move with the times and adopt a slew of new technologies, driven by the requirements of the communications and consumer-electronics industries.

Mentor Graphics is a world leader in design tools for the PCB industry, enabling, in particular, high-speed design techniques. DigiTimes.com spoke recently with David Wiens, director of Business Development, Systems Design Division, Mentor Graphics, about the new technologies and emerging trends in PCB design. Some of them, such as high-density interconnect (HDI) technology, are here to stay. Others are still a gleam in the eye of R&D.

This is the first part of a three-part interview. Part II will follow on 7 November. Part III will follow on 8 November.

Q: With increasing demand for consumer electronics, and mobile handsets in particular, we've seen the rise of flex and rigid-flex PCB production. What are the advantages, issues and design challenges posed by FPC production?

A: Flex technology is becoming much more important as manufacturers of mobile handsets switch from the classic brick-type designs to clamshell formats, which require flex boards. Even so, flex technology has been predominant for years, particularly in the Japan market, for cameras and other devices.

From a design challenge perspective, it requires the ability to partition the design from what used to be a single PCB into multiple PCBs that then fit into an overall enclosure. So, where before you had a typical brick phone, now you’ve got multiple elements, each of which may sit, via connectors, on multiple boards. Each of these boards may have different layer counts, and each has to be managed as a different partition of a common design. Just as in some types of systems design, a designer may have to decide where to place the logic – in the silicon or on the board – flex designs complicate that partitioning further.

Clearly, flex board designs are application dependent. There is not a lot of flex inside a PC, for example. It isn’t necessary. On the other hand, telecom customers, phone manufacturers, are increasingly asking for flex boards. These are the industries that see advantages in using flex PCBs. Any application where size is a challenge will see flex regarded as a possible alternative.

But flex isn’t always the best alternative from the performance perspective. When trying to integrate functional blocks, with critical signals operating at speed, the signals need to be shielded appropriately and managed for controlled impedance to ensure signal integrity. That’s why optical interconnects between those functional blocks can sometimes be a viable answer, although it’s not cost-effective in consumer electronics.

Signal integrity constraints can also dictate when to use flex and where you should partition your design. The general design strategy is to put all critical signals in one area, one functional block. For instance, a phone might have all of its critical I/O, or all of its critical RF signals in one functional block, and the less performance-critical signals in another area. All the keypad and screen functions may be located on the reverse side of the PCB, for instance.

Q: What are the advantages, issues and design challenges posed by the use of embedded passives in PCB fabrication?

A: The use of embedded passives saves space on the board; they can reduce the overall size of a board, and that is a form of cost reduction because you can get more boards on a panel. But embedded passives also incur manufacturing costs, and these are recurring (per-board) costs. You will also have capital equipment costs – additional test and trim tools for example.

Additional material layers are required, which will increase the cost of the laminate structure. Additional manufacturing steps are needed, which will drive up design-cycle time and cost. Embedded passive elements must be etched; they’ve got to be trimmed to value (typically with a laser); and they’ve got to be tested – all of this is an investment in time. So you really don’t take on this technology unless you need the space savings.

But even though use of embedded passives increases manufacturing costs, you can actually recoup those costs, as a result of savings in board space and component assembly. Getting rid of all the surface-mount devices saves you enough money, in terms of assembly cost and component costs, to outweigh the costs incurred during fabrication.

The other challenge is from a designer productivity perspective, where the designer has to take a look at this technology and figure out a way to integrate it into the production process. You’ve got to look at different ways to create components; you’ve got to find different ways to place those components on the board, test them, and output them to manufacturing. So there are some additional steps that recur on a design-by-design basis.

The proponents of this technology would say that its advantages far outweigh any of the issues and challenges. It results in increased board density, a primary benefit. And it can actually reduce costs – you can implement this technology more cheaply than you can surface-mount technology. Gains in performance are another primary benefit because these components are situated directly beneath the active device, so you don’t have any additional inductive loops or delays for resistors, for example, and the same thing applies with decoupling capacitors and the power source. In addition, using laser trim techniques, a resistor can be tuned to within 1% of value. You also don’t have to select an existing component – a 10-ohm or 25-ohm component say – you can design an 11.5-ohm embedded resistor to exactly match the required line impedance.

The reliability of embedded passives tends to be higher. You don’t have component failures due to tomb-stoning during the assembly process. There are also fewer issues with yield.

The laser trim technique is roughly analogous to squeezing a hose to increase the pressure of water – trimming into a resistor impedes the current flow, increasing resistance. The trim technique dates back to the 1970s, but at that time it was only available for use on ceramic substrates and was not widely adopted. Now it’s available for use on laminate structures.

From a design tool perspective, we can handle embedded passives today. We’ve integrated it into our core flows, and it’s an add-on module. Then designing in embedded passives just becomes part of the flow – just like any other component. But because these embedded passives are dependent on materials, it’s not like planning for a consistent resistor size per value in every design. The resistance of the resistor may change based on material resistivity, and the dielectric constant of the laminate or the solder mask. From that point of view, passive components are very design dependent, and that changes the design process.

This is the first part of a three-part interview. Part II will follow on 7 November. Part III will follow on 8 November.

David Wiens, director of Business Development, Systems Design Division, Mentor Graphics

Mentor Graphics’ latest tool for PCB design is Expedition Enterprise.

Part two

Chris Hall,                                                                                   DigiTimes.com, Taipei [Monday 7 November 2005]

The downturn of late 2000 to 2002, coupled with high levels of capital investment, placed many PCB companies in a bind. Those that have survived have been the companies best able to move with the times and adopt a slew of new technologies, driven by the requirements of the communications and consumer-electronics industries.

Mentor Graphics is a world leader in design tools for the PCB industry, enabling, in particular, high-speed design techniques. DigiTimes.com spoke recently with David Wiens, director of Business Development, Systems Design Division, Mentor Graphics, about the new technologies and emerging trends in PCB design. Some of them, such as high-density interconnect (HDI) technology, are here to stay. Others are still a gleam in the eye of R&D.

This is the second part of a three-part interview. Part I appeared on 4 November. Part III will follow on 8 November.

Q: With the increasing emphasis on complex systems designed into small physical spaces – as with mobile handsets and a wide array of consumer devices – we've seen the rise of HDI fabrication and the use of microvias, and so on. What are the advantages, issues and design challenges posed by the use of HDI techniques?

A: HDI again involves additional time and cost. Like embedded passives, there are additional manufacturing steps. You’re going through a deposition of materials onto the core laminate structure, then etching of the interconnect and via creation. Laser drilling is just one of many options for via creation – a lot of times they are etched. Manufacturers will use an etch technology for HDI very similar to that used for silicon.

HDI technology is, in fact, completely borrowed from silicon, which is why, of course, it costs more. Whereas people are designing embedded passives onto laminates because they have found a way to do it cost-effectively, HDI is still, comparatively, an IC process. Designers have for years weighed the costs of going to smaller drilled vias on a PCB versus the cost of going to HDI. Smaller dimensions and a smaller drilled via are viewed more as incremental steps than is adopting the HDI process on top of a laminate structure. But the smaller the drill goes, the greater the chance of it breaking, and a broken drill means longer manufacturing time.

Vias that have been made using a drill – either a mechanical drill or a laser drill – tend to have a purely cylindrical structure, whereas vias that have been etched have more of an intricate structure. There is a large number of possible via structures, and the fact that so many exist in itself inhibits adoption because the designer has to go through a decision-making process as to which one to adopt, and that in itself might depend on the particular capabilities of a company’s target fabrication houses. So the lack of standardization is inhibiting, which is why the IPC is documenting some of them – they hope the industry will stick to the documented structures. Note that the increased cost of HDI fabrication can be weighed against the resulting reduction in board size and layer count – overall, the cost per panel may actually be cheaper with HDI.

Designing HDI via structures differs from designing through-hole structures. With a through-hole structure, you can only locate vias where you are able to drill, depending on the laminate structure. With HDI, you can create a hole through any two layers, and sometimes the holes can be directly on top of each other; and sometimes they may have to be staggered apart. All of these become criteria based on the manufacturing process you are going to utilize. That’s why when implementing HDI technology, designer productivity is going to take a hit because it involves additional constraints. It also changes routing algorithms; some routers are better at handling HDI than others.

With HDI, you are also looking at limited fab infrastructure, particularly in North America. Certainly there are some fabs that have been built incorporating processes for HDI, but you’ve got to select your target fab before you start design. You have to collaborate with the fab on the design constraints. In practice, this means you have to shop for fabs, and you have to say, OK I’m thinking of doing HDI, and I’m thinking of doing this particular kind of HDI, so I can only shop between a limited number of fabs. Then your enterprise is going to tell you that the fab costs too much. You only use them when you have very performance-critical or space-critical designs.

It becomes a trade-off. You are sitting there working with the design side, the manufacturing side and the enterprise side, to determine which approach can be used for which design. It becomes an additional set of variables to consider. No one solution fits all designs.

Q: Another design trend is to printed conductives. Can you outline the type of implementations involved, the advantages, issues and design challenges?

A: Printed conductives are a variant borrowed from hybrid design. They used to be called crossover traces. With printed conductives, the crossovers are now being implemented on a laminate structure. You have your normal copper trace routes, but instead of creating an additional laminate layer to get over an obstacle, you just put a little localized dielectric bridge down, and then run the trace right over the top of that. It’s a simple process and that’s why it was created in the hybrid days – it was also a form of cost reduction. Instead of creating a new material layer, you just localized that material in a particular region.

From a design tool perspective, it’s a little bit harder to design boards with printed conductives, but pretty much anyone could kludge it. We do have a tool that knows how to do them pretty well, with an automated methodology. It’s the sort of thing where someone could adopt a technology without changing their tools, but it’s a question of how efficiently the designs could be done.

Q: Why a question of how efficiently?

A: Because it’s a lot like HDI. If a tool doesn’t know what HDI is, a designer can fake it depending on how smart the tool is. If the tool looks at, say, a four-layer structure and says, you can’t create a via between layers two and three because it knows you have a laminate structure, and that’s not allowed, well then, you’re out of luck. If the tool says, instead, you really shouldn’t do that, but it’s going to let you do it, then you’ve found a way to kludge it and get the job done.

The same thing goes here. How do you design without a specific tool capability? You would just add an extra layer. What used to be Layer One is now Layer Two, and an extra layer is created on top. But when that data is extracted, you would have to know you’re not actually creating an extra laminate layer. The opposite of kludging an HDI structure or a printed conductive with a design tool is automation. Automation enables effective constraint definition, facilitates creation of the design elements within layout as well as design constraint verification, and simplifies manufacturing output of the requisite data.

The printing can be done using a couple of techniques, and one of those could be as simple as a screen-print process. This technology came from the hybrid arena – and that’s where it ties in with HDI, and that’s also where it ties in with embedded passives because the same type of screen-printing technology that is used for some resistors is also used for screen-printing dielectrics and conductives.

Screen-printing, as opposed to etching the dielectric into place, would be an additive process, as opposed to a subtractive process. You add the localized dielectric with the screen-printing process, and then add the conductive on top it, with same process.

A disadvantage is that although the screens have improved a great deal over time, you still have a certain roughness or lumpiness to the printed conductive, especially along the edges, and where you have a thick printed conductive in very close proximity to very fine-line etch, that could affect the characteristics of the circuitry. A printed conductive could alter impedance; it could introduce parasitics. In particular, printed conductives, with their rough edges, are not suitable for high frequencies, and that means, of course, they are not suitable for RF.