The device was due to be described at the International Solid-State Circuits Conference (ISSCC) in San Francisco, in a paper authored by researchers from STMicroelectronics and Hynix Semiconductor. The 4-Gbit chip incorporates a dedicted error-correction processor that can detect and correct as many as five errors per page, ST said.

Multilevel cell (MLC) technology, where each NAND flash memory cell stores two or more bits of data, offers a benefit in density and, therefore, in cost. But the technology suffers from the disadvantage that the data retention and memory cycling performance are reduced compared with single-bit cell (SBC) NAND flash memories. MLC NAND flash memories normally require more complex error-correction code (ECC) circuits.

By implementing a dedicared ECC processor on the memory instead of offloading the requirement to the system processor, the throughput can be considerably enhanced, ST said. The dedicated processor implements the Bose-Chaudhuri-Hocquenghem error correction technique—a system that is widely used in WLAN and other applications where multiple data transmission errors need to be reliably detected and corrected.

“This innovative breakthrough will fast become standard in ST’s two-bit-per-cell NAND flash road map,” said Carla Golla, general manager of ST’s NAND flash memory division, in a statement. “Moreover, we fully expect this type of approach to be implemented as an industry standard feature in 2-bit-per-cell devices, which are rapidly increasing their share of the NAND flash market. This method realizes the cost advantages of multilevel cell technology but without sacrificing system read throughput and reliability.”

The area occupied by the ECC circuitry is 1.3-square millimeters, or less than 1 percent of the total chip area, ST said.