4-Gbit NAND built at 65 nm
Geoff MacGillivray /techonline
Jul 17, 2006
Samsung has established the No. 1 market position in the
top two semiconductor memory markets. But even as the
memory leader, the company is not known for coasting. It
continues to scale memory products aggressively into
advanced geometries, a technique it used to achieve its
current position. The latest example of Samsung's
scaling efforts is the 4-Gbit NAND flash, the first
standalone memory to be manufactured at the 65-nanometer
node. The device has the small- est 4-Gbit die size seen
by Semiconductor Insights to date. That gives Samsung a
cost advantage in the NAND market.
Samsung holds the top position in both the NAND market
(52.9 percent) and DRAM sector (32.1 percent), the two
largest memory markets. In fact, Samsung is more than
twice as large as its nearest competitor in NAND and
nearly twice as large as the second-place manufacturer
in the DRAM space. The NOR market is the only major
memory segment in which Samsung does not hold the top
spot; it was the fourth-ranked NOR manufacturer in 2005,
according to iSuppli Corp.
The secret to Samsung's success is its aggressive
strategy of moving its products into advanced process
technologies as rapidly as possible. By moving quickly
to advanced process technologies, Samsung is able to
manufacture devices with smaller die sizes. Those small
die sizes translate into more dice per wafer and, thus,
lower manufacturing costs--and ultimately, more price
flexibility. The strategy has given Samsung a
competitive advantage in the memory industry that other
manufacturers have been unable to duplicate.
Recent examples of Samsung's technology scaling include
the first 90-nm DRAM, a device that was manufactured
several months ahead of any other 90-nm DRAM. Samsung
will also likely be the first manufacturer to produce
80-nm DRAMs and will be doing so while many competitors
are still ramping volume in their 90-nm process
technologies. It is now very clear that NAND flash
production will take place on much more advanced process
nodes than DRAM. In the NAND market, Samsung was the
first manufacturer to the 70/73-nm node and is now the
first to the 65-nm node. NAND competitors like Toshiba
and Hynix are close behind, however, and have some
technological advantages that help their position.
The Samsung 65-nm 4-Gbit NAND flash (K9F4G08U0A) is a
monolithic device that uses single-bit-per-cell
technology. The device is fabricated using a
triple-metal, double-poly, 65-nm CMOS process on a
131-mm2 die. The single-transistor flash cell measures
approximately 0.126 x 0.13 micron, for a total cell area
of only 0.016 micron2. The overall bit-efficiency rating
is 31.3 Mbits/mm2.
The 65-nm device is 15.9 percent smaller than the
previous 4-Gbit-generation device, which was
manufactured with 73-nm process geometry. However, the
die efficiency on the 65-nm device is 54 percent, down
approximately 6 percent from the 73-nm device. The loss
in die efficiency is likely due to scaling differentials
between the array and peripheral circuitry.
The 65-nm and 73-nm devices share several innovative
process technologies that have been successfully scaled
from 73-nm geometries to 65 nm. These features include a
self-aligned floating-gate poly cell along with similar
control-gate and floating-gate structures. However, the
65-nm device includes some new process techniques to
deal with floating-gate coupling, select transistor
contacts and shallow trench-isolation depths.
The device uses single-bit-per-cell (SBC) technology,
storing only 1 bit per memory cell. SBC technology has
been the standard flash technology for many years and is
easier to implement than multilevel-cell (MLC)
technologies. SBC technology is more reliable than MLC
and requires less testing time. But it suffers some cost
disadvantages compared with MLC implementations because
of the lower density.
The 4-Gbit NAND flash generation is becoming an
extremely competitive area, with several vendors
offering very similar devices. The Samsung K9F4G08U0A
has the smallest 4-Gbit die size that Semiconductor
Insights has observed to date. It is 5 percent smaller
than the next smallest 4-Gbit device, an offering from
Toshiba that is manufactured at the 90-nm node.
Samsung's early 4-Gbit offerings were not as competitive
as Toshiba's 4-Gbit, 90-nm MLC device, and it is likely
that this part was expressly designed to compete with
Toshiba's offering.
The die size advantage offered by Samsung's 65-nm
technology allows the company to manufacture
approximately 469 gross dice per 300-mm wafer. This is
6.4 percent more than the Toshiba 4-Gbit offering and
11.4 percent more than Hynix/ STMicroelectronics' 70-nm
product.
However, Samsung faces stiff competition from both of
those companies. Toshiba is the second-ranked player in
the NAND market, and its strategy is to use MLC
technology to manufacture devices with very high
bit-efficiency ratings in older process nodes. MLC flash
stores 2 bits of information at each memory cell site,
allowing Toshiba to pack more bits into a given area of
silicon and lowering the manufacturing cost for a given
size of memory. The Toshiba 4-Gbit offering is
manufactured at the 90-nm process node and has a
bit-efficiency rating of 29 Mbits/mm2. Toshiba was the
first manufacturer to produce a monolithic 4-Gbit device
and was able to do so with a very effective die size.
This device is now eclipsed only by Samsung's 65-nm
4-Gbit device. Toshiba continues to use its MLC strategy
and now has an 8-Gbit, 70-nm MLC device, the largest
monolithic NAND flash device currently on the market.
Hynix and STMicroelectronics are relatively new entrants
to the NAND flash market but have been able to jump
quickly into the technology race. Their latest offering
in the 4-Gbit generation is a 70-nm single-bit-per-cell
device that has a die size of 144 mm2 and a
bit-efficiency rating of 28.4, a commendable achievement
that positions this new entrant well in the NAND market.
Die size has a direct effect on the manufacturing costs
for the NAND flash devices shown in the table above.
Calculations from a cost model from IC Knowledge LLC
provide estimates of the gross number of dice that can
be manufactured for each device. These rankings mirror
die size statistics and show that Samsung can
manufacture just under 30 more devices per wafer than
the second-ranked device.
Currently, Semiconductor Insights has been unable to
locate 4-Gbit offerings from IM Flash and Renesas
Technology. IM Flash will need competitive offerings in
the 4-Gbit generation in order to compete with the top
three NAND manufacturers. Renesas is producing a 90-nm
4-Gbit MLC NAND but has announced it will not continue
research and development efforts beyond that node.
Samsung has successfully moved its flash technology to
the 65-nm node by addressing several scaling challenges,
including cell alignment, tunnel oxide thickness and
flash cell coupling. Now the company can focus on
expanding its product line at the 65-nm node with an MLC
device and on development at the 55-nm node. Development
of an MLC product will be necessary to compete with
Toshiba's 70-nm MLC device for design slots in
cost-sensitive applications.
The NAND market space is definitely becoming more
competitive, and it is necessary for manufactures to
produce devices in leading process nodes. Samsung,
Toshiba and Hynix/ST are all at or below the 70-nm node,
so it is likely that those manufactures will move
quickly to 65- or 55-nm process technologies. IM Flash
will also need to move quickly to those nodes in order
to be competitive. Therefore, Samsung cannot rest
easily; it must move quickly to widen its product line
and push to the 55-nm node.
Devices at that geometry are currently in development
and are forecast to be in production in late 2006 or
early 2007. They will likely be 16-Gbit MLC devices from
Samsung, Toshiba and Hynix/ST. The 55-nm node will
likely feature cell sizes in the range of 0.0084 µm2 and
initial die sizes between 140 and 160 mm 2. Those
projections are derived from historical die and cell
sizes. The 55-nm devices will share some characteristics
with their 65-nm and 70-nm predecessors but will need to
address some critical scaling areas, such as cell
alignment, tunnel oxide, interpoly dielectric, coupling
between adjacent cells (crosstalk) and high-voltage
transistor design.
Improved alignment between patterned layers is an
obvious and constant concern as devices are scaled down.
Smaller devices demand lower-voltage operation, which in
turn drives the need for thinner tunnel dielectrics for
transferring charge onto and off the floating gate. But
thinner dielectrics are not as reliable. In advanced
geometries, the active area for a floating gate to
influence the cell transistor is smaller, but the
control-to-floating-gate coupling ratio needs to remain
constant. Therefore, a thinner interpoly dielectric is
required. In the case of both dielectrics, a higher-k
(dielectric-constant) material can reduce the effective
electrical thickness while maintaining higher
reliability with a greater physical thickness.
Nevertheless, introducing new materials brings its own
challenges. Packing cells tighter increases the risk of
charges on one floating gate influencing the operation
of an adjacent memory cell. Finally, flash operation
relies on relatively high voltages to program and erase
cells. Control transistors for switching those voltages
need to be kept small so that they don't reduce the
memory cell efficiency for a given silicon area.
Samsung has fielded the first 65-nm memory device in the
market. The K9F4G08U0A is further proof that Samsung
continues to push manufacturing into advanced process
nodes to gain a competitive advantage over other memory
manufacturers. However, process node leadership is not
enough in the cost-competitive memory market, and
circuit techniques such as MLC programming are necessary
to compete in cost-sensitive memory applications.
Now that Samsung has a working 65-nm part, it will
likely focus on expanding its 65-nm line to include an
MLC offering and then push toward 55 nm. |
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