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Ron Maltiel has more than 20 years experience in design and manufacturing of
semiconductor processes and devices such as memories, microprocessors, and
analog devices.
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Inventor of six patents
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Studied semiconductors at Stanford University
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Developed new
processes and devices at Intel, AMI, AMD, and Maxim.
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Experienced in
supporting patents and trade secrets (IP) litigation.
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Operates a
semiconductor technology and patent website.
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Semiconductor
Consulting
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Expert consultant
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Expert witness
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Patent litigation
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Circuits, Processes
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Devices
(CMOS, BICMOS)
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Flash memory
(NAND or NOR)
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EEPROM memory
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DRAM memory
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SRAM memory
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Manufacturing
(Wafer Fabrication)
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Processes
(oxidation gas, polysilicon, plasma, etch, lithography,
diffusion, metal, planarization, grove, trench)
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Process Flow
(Sub-Micron)
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Chip Measurement
(Test Chip)
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Analog
technology
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Digital
technology
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New Process Technology
- TSMC Use a Gate-Last Deposition Process for the High-k/Metal Gate Stack of its 28 nmTransistors
- IEDM 2009 - Will IBM Shift to Gate-Last; Intel 32 nm PMOS; Silicon CMOS for 22 nm; Logic Processes
- How much of a lead does Intel have at 32nm and for High-K Metal Gate (HKMG) Technologies?
- Lithography Manufacturing Beyond 22nm
- IEDM 2009 - NEC, Toshiba, and IMEC Devices
- Semiconductor Industry Trends in Light of 2008 Economic Upheaval
- IEDM 2009 Preview
- Semiconductor IC Ranking Q3 2009 (fast growth at Samsung, Toshiba, Hynix, Micron)
- Intel's 32nm Silicon Technology - Microprocessor and System-on-Chip (SOC)
- Globalfoundries (GF) More Advanced Than TSMC
- Semiconductor Inventory and its Impact on Electronic Supply Chains- iSupply
- Semiconductor IC Ranking Q2 2009(Climbing TSMC, Hynix, MediaTek Droping AMD, Freescale, Fujitsu)
- Samsung- 5 nm is Not a Limit to Silicon Scaling
- VLSI 2009 - Updates
- Toshiba announces high-k/Ge gate stack technology for 16nm
- Tungsten Plug Issues and 32 nm Process
- Scalling to 22 nm Process
- 15 Technology Challenges for 22-nm Node
- 450-nm Fabs Status
- IEDM 2008 - 2nd Update
- IEDM 2008 - Update
- IEDM 2008 Preview
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VLSI 2008 Symposium Highlights
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VLSI 2008 Technology Program
- Low-k Dielectrics Status and 45 nm Process
- Interconnect Issues and 45 nm Process
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TSMC 40nm Process Expected in Second Quarter 2008
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Diode Lasers (LED): New Materials can extend life
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IEDM 2007 Highlights
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Intel's 45-nm High-k Metal-Gate Process
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Intel's 45-nm Process: High-k First, Metal-Gate-Last Integration
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Rapid-Thermal Process of Atomic Layer Deposition Drastically
Reduced Gate Leakage for a High-k Dielectric
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IEDM
Technical Program - 2007
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Intel's High-k Dielectric and Metal Gate Process Solution
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Device Engineers are Reconsidering Germanium Transistor
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Lithography Trends and New Patterning Materials
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Physics of Strained Silicon
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Manufacturing Sub 50nm DRAM and NAND Flash
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SPIE Advanced Lithography Conference -Troubling Signs for
Often-delayed EUV Technology
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Applied claims Two Masking Breakthroughs: Self-aligned Double
Patterning Technology and a Hardmask Systemask System
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Hi-k Dielectric Metal Gate Integration Delays Introduction of
FinFET
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Intel, IBM, NEC announce Hi-k Metal gate Breakthrough
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Process Integration Issues for 45 and 32 nm Technologies
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Enhancing Multi-gate Si MOSFET Performance
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Advanced NMOS and PMOS (CMOS) Transistor Junction Fabrication
for 45nm Node
- Doping, Annealing, Source
and Drain Optimization, Ion Implantation, Spreading Resistance.
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Copper Interconnect for 45nm Process
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Characterization Tools Overview of Copper Metal Interconnect
Integration
- Chemical, Physical, Structural, Electrical, Depth
Profile, Morphology, Surface Pattern.
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Contact-Hole Etch Profile and CD Control Improves by Using a
Polymer - Impact of thinner resist
(PR) layer, Bottom Anti reflective coating (ArF, BARC), and
thinner mask.
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CMP-Chemical Mechanical Planarization
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Post-Etch Residue and Photoresist Removal
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removal of photoresist (PR) in the front-end-of-line (FEOL),
post ion implantation, and back-end-of-line (BEOL) following
etching.
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Gas System - Fluorocarbon (CF4, CHF3) Used for Dielectric
Material
- Etch, Diffusion Issues
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Manufacturable Ultralow-k and Low-k Dielectrics
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Review of Electrical Requirements and Issues with Thermal,
Mechanical, and Chemical Properties of Low-k Interlevel
Dielectric
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Chemical Vapor Deposition (CVD) vs Atomic Layer Deposition (ALD)
for High-k Dielectric
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Process Steps Integration Issues for Metal Gates in CMOS
Technologies
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Process Integration Concerns of High-k/ Low-k, Cu, Metal Gate,
and CVD or ALD Deposition
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Review of Future High-k Gate Dielectrics Including Hafnium
(Hf)-based Materials
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Samsung's SDRAM Process with High-k Capacitor Manufactured by
ALD Process and Recessed Channe Array Transistors (RCAT)
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Hitachi 90-nm Manufacturing Process
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Full Single Wafer
Fabrication
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The International Technology Roadmap for Semiconductors (ITRS)
ITRS_Roadmap for Lithograph and CMP Planarization
- Immersion and Extreme
Ultraviolet (EUV) Lithography, CVD and PVD deposition and
Planarization
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Atomic Layer Deposition (ALD) Manufacturing -
Batch versus Single Wafer, Deposition Temperature, Step
Coverage, Uniformity
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Atomic Layer
Deposition (ALD) Used For Copper Seed and High-k Dielectric
Processes for Logic
and DRAM Products
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ALD Two-step Process Cycle
- Chemical Gas
Injection, Film Thickness, Uniformity, Composition
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AMD, IBM dual-stress liner (DSL) technique for straining both
the NMOS and PMOS transistor channels
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Intel still Leads in 65-nanometer Technology Race, but —
Texas Instruments, Xilinx, and AMD Catching Up
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Self-Aligned SiGe BiCMOS using selective Epi (SEG)
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Activation of Sb during Solid-Phase Epi and Deactivation during
Subsequent Thermal Process

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Update - Apple’s iPhone 3G Semiconductor Parts
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65 nm Process Technology for 3G mobile Applications in Qualcomm
and TI
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Integrated Circuit Technology Challenges
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DRAM memory Transition from DDR2 to DDR3
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Manufacturing Sub-50nm DRAM, Scaling NAND Floating Gate Flash
Memory
- RCAT, 3D
Capacitor, TANOS FG
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Flash
Memory Introduction, Overview, and Scaling -
Flash (NAND and NOR), FRAM, MRAM,
Phase Change Memory
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Hard-disk Drive vs. Flash
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Nonvolatile
Memory NOR vs. NAND from a PC Board User Perspective
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NAND vs. NOR Flash
Memory Technology Overview -
Power and Speed (Read, Write and Erase) Properties for SLC, and
MLC NAND/ NOR vs. Pseudo Static RAM (PSRAM)
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Multi-level
Cell (MLC) NAND vs. Single Level Cell Performance for Consumer
Applications -
e.g. Digital Photography, MP3 Audio Player, USB Drive, and Data
Storage ( Read and Write Speed and Bandwidth Properties)
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Samsung's CTF NAND for 32-gigabit (Gbit) 40-nm Process with
high-k Layer
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New Flash Technologies- PRAM, FRAM, MRAM, and CTF (Charge Trap
Flash using Tanos Dielectric)
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Limit to CMOS Scaling of NMOS and PMOS Transistors
- Strain Scaling of CMOS, Contact Etch Stop Layer (CESL) Process
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Flash Memory Scaling
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Overview of Matrix
Memory three-dimensional antifuse-based, one-time-programmable
memory technology
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X4 (4 Bit / Cell) Flash
NAND Technology
- White paper from M-System
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Status of
Nonvolatile Phase Change Memory OUM (Ovonic Unified Memory)

International Technology
Roadmap for Semiconductor
(ITRS)
2009
2008
2007
2006

Packaging Process Technology
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Film Deposition & Patterning, Silicon Oxidation,
Ion Implantation, and Metallization
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Animated Presentation of Processing Steps Including Cleanroom, Photolithography (Stepper or Scanner), Metrology, CMP
Planarization
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Detailed Wafer Fab Process Steps ( Epi, Diffusion, Oxidation,
Metallization)
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Semiconductor Review of Process, Device, and Circuit Topics
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How to Manufacture a Semiconductor Chip
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Major Fabrication Steps in MOS Process Flow
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Details of Ion Implantation and Links to Many Other
Semiconductor Fabrication, Physics, and Tutorials
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Manufacturing Process Technology - Metal Interconnect
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Manufacturing Process Technology - Silicon On Insulator (SOI))
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Manufacturing Process Technology - Transistor
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Manufacturing Process Technology - Memory
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Deposition, Oxidation, CVD,
Electrodepositing, and Epitaxy
Processes
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Etch Processes
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Lithography Processes
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Improved Resolution in Photolithography with a Phase-Shifting
Mask (PSM)
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Types of Phase-Shifting Mask (PSM)
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Transperent Phase Shift Mask (PSM) Improves Resolution
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Semiconductor Manufacturing Process Steps
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Smithsonian Chip Collection


Technical Database
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