Introduction to Semiconductor Manufacturing Process

• Film Deposition & Patterning, Silicon Oxidation, Ion Implantation, and Metallization

• Animated Presentation of Processing Steps Including Cleanroom, Photolithography (Stepper or Scanner), Metrology, CMP Planarization

• Detailed Wafer Fab Process Steps ( Epi, Diffusion, Oxidation, Metallization)

• Semiconductor Review of Process, Device, and Circuit Topics

• How to Manufacture a Semiconductor Chip

• Major Fabrication Steps in MOS Process Flow

• Details of Ion Implantation and Links to Many Other Semiconductor Fabrication, Physics, and Tutorials

• Manufacturing Process Technology - Metal Interconnect

• Manufacturing Process Technology - Silicon On Insulator (SOI))

• Manufacturing Process Technology - Transistor

• Manufacturing Process Technology - Memory

• Deposition, Oxidation, CVD, Electrodepositing, and Epitaxy Processes

• Etch Processes

• Lithography Processes

• Improved Resolution in Photolithography with a Phase-Shifting Mask (PSM)

• Types of Phase-Shifting Mask (PSM)

• Transperent Phase Shift Mask (PSM) Improves Resolution

• Semiconductor Manufacturing Process Steps

• Smithsonian Chip Collection 

    International Technology Roadmap for Semiconductor

    (ITRS)

• Executive Summary - 2006

• Process Integration, Devices Structures - 2006

• Front End Process - 2006

• Interconnect - 2006

• Lithography - 2006

• Metrology - 2006

• Yield - 2006 

  Packaging Process Technology

• New Trends in Packaging

New Process Technology

• TSMC 40nm Process Expected in Second Quarter 2008

• Diode Lasers (LED): New Materials can extend life

• IEDM 2007 Highlights

• Intel's 45-nm High-k Metal-Gate Process

• Intel's 45-nm Process: High-k First, Metal-Gate-Last Integration

• Rapid-Thermal Process of Atomic Layer Deposition Drastically Reduced Gate Leakage for a High-k Dielectric

• IEDM Technical Program - 2007

• Intel's High-k Dielectric and Metal Gate Process Solution

• Device Engineers are Reconsidering Germanium Transistor

• Lithography Trends and New Patterning Materials

• Physics of Strained Silicon

• Manufacturing Sub 50nm DRAM and NAND Flash

• SPIE Advanced Lithography Conference -Troubling Signs for Often-delayed EUV Technology

• Applied claims Two Masking Breakthroughs: Self-aligned Double Patterning Technology and a Hardmask Systemask System

• Hi-k Dielectric Metal Gate Integration Delays Introduction of FinFET

• Intel, IBM, NEC announce Hi-k Metal gate Breakthrough

• Process Integration Issues for 45 and 32 nm Technologies

• Enhancing Multi-gate Si MOSFET Performance

• Advanced NMOS and PMOS (CMOS) Transistor Junction Fabrication for 45nm Node - Doping, Annealing, Source and Drain Optimization, Ion Implantation, Spreading Resistance.

• Copper Interconnect for 45nm Process

• Characterization Tools Overview of Copper Metal Interconnect Integration -   Chemical, Physical, Structural, Electrical, Depth Profile, Morphology, Surface Pattern.

• Contact-Hole Etch Profile and CD Control Improves by Using a Polymer - Impact of thinner resist (PR) layer, Bottom Anti reflective coating (ArF, BARC), and thinner mask.

• CMP-Chemical Mechanical Planarization

• Post-Etch Residue and Photoresist Removal - removal of photoresist (PR) in the front-end-of-line (FEOL), post ion implantation, and back-end-of-line (BEOL) following etching.

• Gas System - Fluorocarbon (CF4, CHF3) Used for Dielectric Material - Etch, Diffusion Issues

• Manufacturable Ultralow-k and Low-k Dielectrics

• Review of Electrical Requirements and Issues with Thermal, Mechanical, and Chemical Properties of Low-k Interlevel Dielectric

• Chemical Vapor Deposition (CVD) vs Atomic Layer Deposition (ALD) for High-k Dielectric

• Process Steps Integration Issues for Metal Gates in CMOS Technologies

• Process Integration Concerns of High-k/ Low-k, Cu, Metal Gate, and CVD or ALD Deposition

• Review of Future  High-k Gate Dielectrics Including Hafnium (Hf)-based Materials

• Samsung's SDRAM Process with High-k Capacitor Manufactured by ALD Process and Recessed Channe Array Transistors (RCAT)

• Hitachi 90-nm Manufacturing Process - Full Single Wafer Fabrication

• The International Technology Roadmap for Semiconductors (ITRS) ITRS_Roadmap for Lithograph and CMP Planarization - Immersion and Extreme Ultraviolet (EUV) Lithography, CVD and PVD deposition and Planarization

• Atomic Layer Deposition (ALD) Manufacturing - Batch versus Single Wafer, Deposition Temperature, Step Coverage, Uniformity

• Atomic Layer Deposition (ALD) Used For Copper Seed and High-k Dielectric Processes for Logic and DRAM Products

• ALD Two-step Process Cycle - Chemical Gas Injection, Film Thickness, Uniformity, Composition

• AMD, IBM dual-stress liner (DSL) technique for straining both the NMOS and PMOS transistor channels

• Intel still Leads in 65-nanometer Technology Race, but  — Texas Instruments, Xilinx, and AMD Catching Up

• Self-Aligned SiGe BiCMOS using selective Epi (SEG)

• Activation of Sb during Solid-Phase Epi and Deactivation during Subsequent Thermal Process

Product and Device Technology

• 65 nm Process Technology for 3G mobile Applications in Qualcomm and TI

• Integrated Circuit Technology Challenges

• DRAM memory Transition from DDR2 to DDR3

• Manufacturing Sub-50nm DRAM, Scaling NAND Floating Gate Flash Memory -  RCAT, 3D Capacitor, TANOS FG

• Flash Memory Introduction, Overview, and Scaling - Flash (NAND and NOR), FRAM, MRAM, Phase Change Memory

• Hard-disk Drive vs. Flash

• Nonvolatile Memory NOR vs. NAND from a PC Board User Perspective

• NAND vs. NOR Flash Memory Technology Overview - Power and Speed (Read, Write and Erase) Properties for SLC, and MLC NAND/ NOR vs. Pseudo Static RAM (PSRAM)

• Multi-level Cell (MLC) NAND vs. Single Level Cell Performance for Consumer Applications - e.g. Digital Photography, MP3 Audio Player, USB Drive, and Data Storage ( Read and Write Speed and Bandwidth Properties)

• Samsung's CTF NAND for 32-gigabit (Gbit) 40-nm Process with high-k Layer

• New Flash Technologies- PRAM, FRAM, MRAM, and CTF (Charge Trap Flash using Tanos Dielectric)

• Limit to CMOS Scaling of NMOS and PMOS Transistors - Strain Scaling of CMOS, Contact Etch Stop Layer (CESL) Process

• Flash Memory Scaling

• Overview of Matrix Memory three-dimensional antifuse-based, one-time-programmable memory technology

• X4 (4 Bit / Cell) Flash NAND Technology - White paper from M-System

• Status of Nonvolatile Phase Change Memory OUM (Ovonic Unified Memory)

Glossary Links

• Semiconductor Glossary

• Semicyclopedia

• ACRONYMS and Vocabulary Used in Semiconductor Industry

• Fiber Optics Glossary

  Technical Database

• Thermal and Physical Properties Database for Semiconductor Process Gases