Intellectual-Property (IP) Quality in Semiconductors

Most semiconductor IP today is delivered as soft IP - register transfer level (RTL) or configurable generators that produce RTL. IP suppliers do ensure correct functional behavior. Often overlooked in this process is the communication of design intent and implementation feasibility, a task left for the IP consumer to deal with. A poorly designed IP can result in failures at the SoC level with timing, routing congestion, power, clock synchronization, test coverage, etc. Typically these issues will not be uncovered until after a significant engineering effort has been spent on integration of the IP into the SoC and subsequent implementation. The net result is expensive design iterations, project delays and potential silicon failure.

There is clearly the need for some standardization on IP feasibility and quality. Previous efforts in the industry have been unsuccessful for a few reasons:

1. Lack of measurable design intent for soft IP
2. An objective and practical measure of IP quality
3. Lack of automation for 1) and 2)

I propose an approach for communicating design intent and measuring IP quality that is rooted in how design is done. The general premise is to capture good design practices, known design killers and productivity detractors into a knowledge base that spans coding guidelines, synthesizability, connectivity, portability, interfaces, timing, congestion, power, clocking, testability, etc. This knowledge base should be accumulated over a large sample of existing and new designs, and should continue to evolve as new issues are uncovered. The knowledge can then be deployed in a set of intelligent rules and engines that can detect and analyze such issues for a particular IP. Each such rule can be weighted based on a combination of factors - severity of the issue, likelihood of occurrence, possibility of detection, time to detection and correction, number of downstream tasks impacted (e.g., verification, chip integration, synthesis, place and route, etc.). This approach forms the basis of an "IP Quality Score", a quantifiable measure rooted in actual design. Similarly, design intent can be captured and communicated in the form of target specifications for area, timing, congestion and power, as well as in the form of applicable design waivers or exceptions for that IP.

This bottom-up approach to IP design intent and quality is both practical and evolutionary in nature, since the design knowledge base will continue to evolve with new designs and processes. It yields immediate advantages for both the supplier and the consumer of the IP and the overall semiconductor supply chain.

For the IP supplier, the benefits are:

• Target marketing - The design rules and specs can be configured for specific market segments or customers
• Objective handoff - A quantified measure of the IP quality based on agreed upon metrics between the supplier and consumer is now possible
• Transparency - Visibility into the inherent quality of the IP and programmed communication of design intent is provided
• Actionable feedback - The underlying rules and reports can provide the basis of improving the IP Quality Score if required

• IP screening - Screen incoming IPs and compare them based on their relative scores
• Visibility and risk management - A clear understanding of potential risk areas with the incoming IP which need to be avoided or corrected during implementation
• Continuity - The ability to mandate or influence the quality metrics and manage a smooth integration of the IP

About the Author:
Piyush Sancheti, is Senior Director of Business Development at Atrenta Inc.

Lack of standards, quality metrics and business models have hurt the IP industry for years. Profitability remains elusive for many IP vendors. And most--if not--all of those problems continue to haunt the industry as a whole.

At the GSA IP conference here this week, two chip makers--Intel Corp. and Chartered Semiconductor Manufacturing Pte. Ltd.--took turns in separate presentations and landed some pot shots at the semiconductor IP industry for those and other reasons.

"Customers are aggravated and frustrated with the business models," said Walter Ng, vice president of design enablement alliances with Singaporean foundry provider Chartered, during a presentation at the event.

"There is a problem with the third-party IP vendors in terms of scaling," Ng said. And in terms of IP quality standardization, ''there is a lot to be done in that area."

Ng did not identify which IP vendors are dragging down the industry, nor did he point the finger at one company.

Clearly, some IP houses are better than others. Deserved or not, the industry as a whole is to blame for the shaky--if not poor--reputation in the large and complex IP sector. In total, there are 300-to-400 semiconductor IP vendors of all shapes and sizes. ARM, Cadence, MIPs, Rambus, Virage and Synopsys are among the bigger players, but most IP vendors are small-sized shops.

Semico Research Corp. projects that the IP market will grow 18 percent through 2012. The IP business is expected to grow faster than the overall semiconductor industry, said Jordan Selburn, an analyst with iSuppli Corp.

But after three years' of double-digit growth rates, the IP market settled back to 8 percent growth during 2007, according to Gartner Inc. ''Moreover, as growth rates decline, we believe that small to midsize IP vendors should prepare to acquire other companies, or be acquired, as consolidation has become IP vendors' key strategy for gaining scale and remaining in the market,'' according to a recent report from Gartner.

Without a doubt, semiconductor IP remains critical for the industry to enable new designs. But after years' of talk and promises, the IP community is still unable to get its act together.

There is a ''positive trend'' in terms of the evolution of better IP quality, but some vendors still lack good integration practices, said Ken Tallo, director of external IP and virtual platforms at Intel, during a separate presentation at the event.

"Good design practices are not enough'' in the IP industry, Tallo said.

The ongoing problem is deciding what IP has been actually validated and integrated in the design flow, he said. And there are several ongoing and nagging issues with IP: common ABIs, verification and behavioral models, he said.

In the IP community, the verification methodologies ''are not consistent,'' Tallo said. Finding predictable system-level behavioral models are ''also a challenge.''

As a result, chip makers and IP vendors have been calling for standards in the last several years. And the time is still ripe for standards. "It's time for the IP users to align on a common set of integration standards,'' he said.

IP vendors must also step up to the plate. "There are a lot of IP vendors doing the same thing," Chartered's Ng said. "I see a lot of IP companies that don't take risks."

The solution? At least one solution is that IP vendors must ''come out of their silos'' and ''collaborate'' to ''become more competitive,'' he added.

One vendor defended the IP community. "We've made a lot of progress as an industry,'' said John Chilton, senior vice president of marketing and corporate development at Synopsys Inc.

Adam Traidman, group marketing director at Cadence Design Systems Inc., said the IP vendors themselves are moving towards better and more ''flexible business models.''

Over time, IP has been easier to integrate and has seen a shift towards higher-quality products, he said. Traidman was the boss of Chip Estimate. Recently, Cadence acquired IP reuse specialist Chip Estimate.

The industry is also making progress in terms of metrics. Last year, for example, the GSA (formerly Fabless Semiconductor Association) announced the release of its IP assessment tool. The product, dubbed the Hard Intellectual Property (IP) Quality Risk Assessment Tool version 3.0, collects information about an IP vendor and its design methodology.

Snyposys' Chilton also pointed towards the TLM-2.0 standard as another key IP effort. The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to defining and advancing SystemC, recently announced Tallo as the new chairman. SystemC is a language built in C++ that spans from concept to implementation in hardware and software.

In December 2007, OSCI released a second draft of its Transaction-level Modeling Standard (TLM) 2.0 standard. The proposed standard is claimed to assure interoperability between IP models, system models and system-level design tools.

In June, the OSCI announced the completion of TLM-2.0. The TLM interface standard enables SystemC model interoperability and reuse at the transaction level, providing an essential ESL framework for architecture analysis, software development, software performance analysis, and hardware verification.

"TLM-2.0 addresses the real-world interoperability of transaction level models," Tallo said in a recent statement. "It helps streamline the integration of models from different suppliers without compromising their simulation speed, while allowing for continued advances in TLM performance, productivity and usability. OSCI members and SystemC users from around the world have an active role in the standardization process and are now working diligently across the ESL ecosystem to incorporate TLM-2.0."

In a somewhat rival effort, Mentor Graphics Corp. and Cadence this month announced the release of the latest version of the open-source Open Verification Methodology (OVM). OVM 2.0 includes the new OVM User Guide, which provides step-by-step guidelines to help users develop reusable, interoperable verification IP and hierarchical environments to facilitate plug-and-play verification. The Open Verification Methodology, based on IEEE Std. 1800-2005 SystemVerilog standard.

The new release extends the proven sequential stimulus mechanism in the OVM with TLM interfaces to improve the modularity and reuse of stimulus sequences. Other enhancements include direct support for parameterized classes in the OVM factory and built-in debug support for TLM connections throughout the hierarchy.

''The release of version 2.0 of the OVM is a significant event for verification teams,'' said Tommy Kelly, CEO of Verilab, in a recent statement. ''It builds on the previous release of the methodology, further enhances the capabilities of engineers interested in reusable, interoperable verification environments, and strengthens overall the case for using the OVM. Verilab is deploying the OVM in its own verification IP development, and supports the use of the methodology at several of its international clients.''

Another group, the Spirit consortium, a non-profit organization developing an XML based metadata standard to allow multiple facets of a circuit block to be defined, in March announced that it was ready to move the standard up from the register transfer level (RTL) to support transactional and mixed modeling styles.

The move from version 1.2 to version 1.4 also involved the definition of an additional interface known as the tight generator interface (TGI).

The IP-XACT specification, an XML databook that documents many different aspects of IP modules, enables designers to create many different expressions of a design automatically and in a consistent way. Spirit officers emphasized at the show that one metadata starting point can benefit both design and verification engineers.

Still another group, the OCP International Partnership Association Inc. (OCP-IP), in May announced the release of OCP 2.2 Revision A. The latest version of the specification now includes several consensus profiles. Consensus profiles provide company engineers with standardized configurations of OCP options for specific system use cases, ensuring interoperability without conversion, increasing productivity and speeding time to market.

The OCP-IP promotes and supports the Open Core Protocol (OCP) as the complete socket standard ensuring rapid creation and integration of interoperable virtual components.