Ron@Maltiel-consulting.com - Semiconductor & Patent Expert Consulting
Litigation
expert consultant and patent expert witness for process, device, and circuit of Dynamic
Ram (DRAM ), Flash (NAND,
NOR , EEPROM), and Static Ram (SRAM ) Memories,
and Microprocessor, Logic,
and Analog Devices.
TSMC says immersion litho ready to roll
Taiwan Semiconductor Manufacturing Co. said this week that the defects they are seeing with immersion lithography, a technique for drawing circuits on wafers which involve submerging the wafer in water, are well within acceptable limits.
As a result, TMSC will likely start using the process when it starts making 45-nanometer chips, which should come out in 2007 or 2008.
"Our goal is always zero defects," said Burn Lin, senior director of TSMC's micropatterning division in a prepared statement. "Recently, TSMC produced multiple test wafers with defects rates as low as three per wafer -- better than any other immersion results to date, and comparable to the very best dry lithography results. With defect root causes understood, TSMC can now focus on throughput improvement for high-volume manufacturing."
TSMC is the world's first, and still largest, foundry. Foundries make chips
for those that don't have their own factories. Although
Posted by Michael Kanellos