Taiwan packaging and testing industry

Ethan Chen and Rodney Chan, DIGITIMES, Taipei                                                            [Wednesday 12 September 2007]

The momentum driving growth in Taiwan's packaging and testing industry in 2005 continued in 2006, during which seasonal effects were not as obvious as usual. In 2007, the packaging market is expected to have a double-digit growth. But what are the latest trends and problems for the packaging and testing sector?

Outsourcing of back-end services growing

According to Dataquest predictions, the packaging market will continue to grow in the next few years to US$68.03 billion in 2011 from US$37.77 billion in 2005 at a compound annual growth rate (CAGR) of 9.1%. But a breakdown between integrated device manufacturers (IDMs) and dedicated packaging and testing players shows that the IDM packaging market will only have a much lower CAGR of 6.9% from US$22.6 billion in 2005 to US$34.91 billion in 2011. This will be a result of better growth in the outsourcing segment than the overall backend service market. The outsourcing segment will see a CAGR of 11.7% from US$15.17 billion to US$33.12 billion in 2011.

The driver of growth for the outsourcing segment is coming partly from the overall growth in the semiconductor industry, and partly from the rising costs for packaging and testing equipment, which has constrained expansion among IDMs. For example, a mainstream DRAM tester, the T5593 (with a maximum frequency of 1066MHz for DDR and DDR2) costs NT$200 million (US$6.2 million). When the market migrates to DDR3, the utilization rates for the equipment will, in turn, become lower.

It takes about US$3 million to install a TSOP (thin small outline package) line with a monthly capacity of one million units. But it takes more than double the sum – US$8 million – to install a flip chip (FC) packaging line with the same capacity. And there are extra costs for solder bumping equipment for the FC process, which can drive investment costs up another two orders of magnitude. A solder bumping line with a monthly capacity of 5,000 wafers will require an investment as high as US$300 million to build.

With equipment costs rising and IDMs seeing their budgets constrained, most chipmakers are choosing to forsake investments in their own packaging and testing capacities. They are now leaving back-end manufacturing, which is the least profitable area for IDMs, to packaging and testing specialists. The IDMS are selling their packaging and testing plants, investing in packaging and testing companies, or forming joint ventures with them. For example, Advanced Semiconductor Engineering (ASE) has taken over a controlling stake in NXP's packaging and testing plant in Suzhou, China, and Intel has invested in Powertech Technology Incorporated (PTI). According to Dataquest, in 2001 IDMs only outsourced 28.7% of their packaging and testing needs, but by 2011 the percentage will reach 48.1%. This will be good news for Taiwan's packaging and testing sector.

Source: Dataquest, March 2007

Growth to be determined by capex and inventory

Although the global packaging and testing market will in general trend upwards in the long term, short-term fluctuations can be expected. An evaluation of the market should be based not only on the book-to-bill ratio for the back-end equipment market, but also on players' capex plans and the industry's inventory levels.

The book-to-bill ratio has long been a chief indicator of the semiconductor market. Moreover, the book-to-bill ratio for the back-end equipment market in particular has been a bellwether indicator for trends in the overall semiconductor equipment market. The book-to-bill ratio for packaging and testing equipment started to rebound in June 2006, and in March 2007 it climbed to over 1, and further to 1.1 in June. But does it mean that the road lying ahead will be smooth?

It may seem so considering the decreasing investment pressure and rising margins for the top-four players in the packaging and testing industry. But this may be deceptive. Take the capex budget of ASE and Siliconware Precision Industry (SPIL), for example. Their capex budgets have been declining after peaking in 2000. The capex budgets have decreased to about 10% of their revenues in 2007 from over 50% in 2000. The decreasing capex, while relieving the companies of investment pressure, can be seen as growing caution by the top players about capacity expansion. Their strategy of quick capacity expansion has succeeded in boosting their market share, and it is now time to enjoy high margins as depreciation and amortization for equipment draws to a close.

But the top players may be a bit too complacent. In 1999, the top-four players had a combined 43% share of the market, and their capex totaled US$2.06 billion, or 50% of the capex for the entire packaging and testing market. It marks the historical peak of spending by the top players for expansion. In 2006, the top-four players saw their combined market share rise to 49%, but their capex budgets for 2007 amounted to only US$1.21 billion, or 40% of the industry's overall capex for the year. It means minor players are more actively expanding than the giants.

Source: Prismark, April 2007

Source: Prismark, April 2007

Source: Gartner, June 2007

Inventory levels form another issue. Inventory piles up when output from foundries outpaces market demand. The result is that foundries will reduce output, and in turn will cut orders for packaging and testing thereby reducing revenues for packaging and testing companies.

According to iSuppli, semiconductor inventory rose to US$6.6 billion in the second quarter of 2007 from US$6.1 billion in the previous quarter. Most of the increases in inventory resulted from chip suppliers' building up their own stock in anticipation of the high season in the second half of the year, while inventory levels at downstream clients remained low. The clients would only buy chips when necessary, instead of letting their own inventories build up. This implies that chip suppliers had little information about the market situation, and would only find out at the very last moment whether or not their inventory build-up was a waste of time and money. Weaker-than-expected demand will always hurt not just the chip suppliers, but also the packaging and testing sector.

Source: iSuppli, August 2007

Taiwan leadership to remain firm

Taiwan's packaging and testing sector had a strong year in 2006. Seasonal cycles were not obvious, and quarterly revenues stayed high and stable throughout the year on strong demand from the communications and consumer electronics markets. Demand for low-cost applications from emerging markets also drove the low-end and mid-range packaging segments, which helped maintain utilization rates for the industry.

The production value of Taiwan's packaging segment totaled NT$210.8 billion in 2006, up 18.5% from 2005. Its worldwide market share reached 51.2%, the first time that Taiwan has taken more than half the market. The top-five packaging companies accounted for about 70% of the production value of Taiwan's packaging industry in both 2005 and 2006. Minor players, with a 30% share, have mostly focused on the niche market.

For the testing sector, a memory testing capacity shortage throughout 2006 drove sales for IC testing up more than 30%. The year saw players in the memory segment quickly expand their DDR2 capacity, migrate to more advanced processes, and sharply increase their output. The tight testing capacity drove up testing quotes and naturally the production value of Taiwan's testing sector. Taiwan players accounted for 62.5% of the worldwide testing market in 2004, and the share rose to 63% in 2006, with their production value for last year totaling NT$92.4 billion, up 37% from 2005.

Source: IEK, March 2007

Rosy outlook for 2H 2007

Taiwan's packaging and testing industry can be divided into three segments: the traditional (PC, communications, and consumer electronics), driver ICs, and memory. The three segments faced different difficulties in the first half of 2007. The memory segment saw memory prices fall sharply and the driver IC segment was hit by the slow LCD market and high inventory levels. But in general the packaging and testing industry will see a stronger second half in 2007, with some players already reporting an early start of the peak season.

The development of the traditional segment during the second half of 2007 can be observed through the sales and utilization rates of the top foundries, Taiwan Semiconductor Manufacturing Company (TSMC) and United Microelectronics Corporation (UMC). Since the second quarter of 2006, the foundry industry has faced pressure coming from inventory adjustments by PC and consumer electronics clients. Utilization rates at TSMC and UMC declined to 82% and 70%, respectively, in the first quarter of 2007.

The first quarter of 2007 was the low point of the industry's business cycle, but sales started picking up in the second quarter. TSMC posted record high revenues for July, while UMC managed to see monthly sales return to the NT$10 billion level in July – the first time since October 2004. The figures show that the foundries are rebounding into the high season. Their utilization rates are on the rise, which in turn is boosting demand for back-end services.

Memory prices stabilizing

Over the past few years, the DRAM industry has undergone some major changes. When the market migrated from DDR to DDR2, packaging houses had to adjust from TSOP (thin small outline package) being the dominant process to BGA (ball grid array). This year, Microsoft released its Windows Vista operating system, which has greater DRAM needs to support its increased AV functionality. According to IC Insights, the average PC will contain 1.4GB of DRAM this year, an increase of 75% over 2006, when memory per PC averaged 800MB.

The competitive edge of the memory segment hinges on the ability to reduce production costs. One way to reduce costs is to raise yields. Makers can also adopt advanced process technologies, or they can spread the costs by expanding their capacity and output. Judging from Taiwan DRAM makers' expansion plans, in the next two to three years worldwide bit-growth for DRAM and NAND flash will remain at 50-60% each year, which will, in turn, boost memory back-end service demand.

However, with the scope of memory applications expanding, memory players are not just relying on the PC market alone. Demand from consumer electronics applications is growing strong, sending packaging and testing houses scrambling to expand their share of the memory market.

Memory makers are also forming strategic alliances with packaging and testing houses. Powerchip Semiconductor Corporation (PSC) has teamed up with ASE to set up the memory packaging and testing house Power ASE Technology. Elpida Memory has established a fully-owned subsidiary, Akita Elpida Memory, in Japan to handle back-end processes of memory production. The company was created by acquisitions from Hitachi and its subsidiaries.

ASE and SPIL used to have a rather insignificant role in the DRAM segment, which had been dominated by Powertech Technology Incorporated (PTI), ChipMOS Technologies, and UTAC Taiwan. But having seen the profits of these competitors rising, now ASE and SPIL are trying to flex their muscles in the DRAM segment.

Source: iSuppli and IBT, August 2007

However, compared to ChipMOS and PTI, each of which has more than 20 high-speed T5593 testers, ASE and SPIL have only four each. Although ASE and SPIL may not be a threat in the short term, their competition in the long run will be strongly felt by the current top players in the memory segment.

DRAM packaging and testing quotes declined 5-7% in the second quarter because of drops in memory prices, and prices may slide further in the third quarter, stabling DRAM prices and increased output will help raise testing utilization rates to 90% in the third quarter from 85% in the second quarter, while packaging utilization will remain flat.

Driver IC growing strong

The packaging process for driver ICs can be divided into two stages – gold bumping and packaging. Gold bumps serve as the interconnections between chips and tapes in tape-carrier packaging (TCP), chip-on-film (COF) packaging, and the glass substrates in chip-on-glass (COG) packaging.

As COF allows for thinner and more flexible packages than TCP, it better meets the growing demand from consumer electronics for integrated and smaller chips. Therefore, COF is now widely adopted for large-size panels, replacing TCP as the mainstream driver IC packaging process for large-size panels.

As for COG, the driver IC is directly mounted on the panel. Since it is difficult to remount the IC, an error in the mounting of a single IC may result in the waste of the whole panel. The relatively riskier COG is more demanding in terms of yield. It is adopted chiefly for small-size panels that require fewer driver ICs. Currently in Taiwan only AU Optronics (AUO) uses COG in some of its large-size panels.

After a series of mergers and acquisitions in recent years, the driver IC packaging and testing segment is highly concentrated. International Semiconductor Technology (IST) in September 2003 purchased eight driver IC packaging and testing lines from ASE. Chipbond Technology in September 2005 merged with Aptos to become the world's biggest gold bumping service supplier with a monthly capacity of 200,000 units. In April 2006 Chipbond merged with WSE Corporation to strengthen its COG lines. IST in October 2006 merged with gold bumping provider Megic, and claimed that it would become the second largest gold bumping service provider with a monthly capacity of 140,000 units.

Source: KGI, June 2007

Currently the top-three LCD driver packaging and testing players are Chipbond, IST and ChipMOS, all of whom have a capacity much bigger than their smaller competitors. But Chipbond and IST are the only two players who have considerable COF/TCP and gold bumping capacity that allow them to provide turnkey solutions.

The LCD driver IC sector is rebounding from a previous over-supply. With strong demand for COF, Chipbond and IST have been running at a 90% utilization rate for the segment. Although gold bumping utilization remains low at 65%, the two companies' overall margins are improving.

Source: Companies, compiled by Digitimes, August 2007