Austin, Texas -- Texas Instruments Inc. technology executives gave a detailed description of the company's 45-nanometer process technology generation last week. While TI will make several materials changes at the 45-nm node, which will come to market in about two years, the company will stop short of introducing a high-k dielectric.

Hans Stork, senior vice president of silicon technology, said a doubling of transistor density, rather than raw perform- ance improvements, is the primary advantage of scaling from the 65-nm to the 45-nm generation.

"The doubling in transistor density [compared with 65 nm] means we can add functionality, to support more standards in mobile phones, for multimedia or for watching higher-quality video," Stork said.

The smaller transistors also have smaller capacitances, which can work to reduce power consumption. Ben McKee, a TI vice president in charge of the 45-nm development team, said the low-power transistor will have a nominal power supply of 1.1 volts, with operation ranging from 0.9 to 1.2 V. That is a 100-mV reduction from the power supply at the 65-nm node. A 10 percent reduction in V_dd will result in a 20 percent power savings at the transistor level.

TI said its 45-nm SRAM cell size is 0.24 square micron--half the 65-nm generation's cell size. That compares with 0.346 square micron for Intel Corp. (see Jan. 30, page 1). But the fact that SRAMs can be optimized for either performance or density accounts in part for the cell-size variations among companies.

"The drama at the 45-nm node will be behind the curtain," said Rob Lineback, a Dallas-based analyst for IC Insights (Phoenix). "It will be all about how difficult it may be to get good yields. I think that is what is pressing on people's minds."

While TI has relied on foundries for roughly half of its digital CMOS production, Lineback said it may have to reverse course and do more 45-nm production in-house, largely to avoid production glitches at its foundry partners. "The 45-nm node is going to be much tougher than the 65-nm node, with several new materials. But if TI can get to high yields and high volumes, it could give them a tremendous advantage in the high- volume cell phone chip market," he said.

While TI has turned to foundries more often in recent years, it "still pushes the equipment vendors harder than just about anybody, including Intel, when it comes to technology," said Dan Hutcheson, CEO of VLSI Research Inc. (Santa Clara, Calif.). "Their equipment orders are not as large as they used to be, but they seem to have a very long lead time on how technology will evolve. That makes it very valuable for the equipment vendors to work with them, because what they do tends to be the right way to go and gets inserted later at other companies."

High-k not ready
TI will use a conventional gate stack of nitrided silicon dioxide and a polysilicon gate for both its low-standby-power process (for cell phones) and its high-performance process for (digital signal processors). For a 45-nm process developed to manufacture microprocessors for Sun Microsystems, TI plans to introduce a metal gate electrode to reduce the polysilicon depletion effect, which degrades the oxide's electrical performance. It has not decided whether to use deposited metal gates or to create the gate electrodes using a fully silicided method.

At the 32-nm node, TI plans to combine the metal gate with a high-k dielectric. "We are stepping our way up the learning curve, one step at a time," Stork said.

The problem with high-k dielectrics, he said, is that a fairly thick interfacial layer of silicon dioxide must be deposited between the dielectric and the silicon channel. That interface is necessary to maintain reliability and to reduce the mobility degradation that tends to come with metallic dielectrics, such as hafnium oxide.

Stork said limitations on scaling the electrical thickness of the gate oxide make it difficult to reduce the channel length, "since the two dimensions are closely related. The first-order limitation to scaling the gate length is the oxide thickness."

Inflated expectations?
Scott Thompson, an associate professor at the University of Florida (Gainesville), said the semiconductor industry may be placing too many expectations on high-k. To avoid mobility degradation, an interfacial layer as thick as 7 angstroms may be needed, he said. That will reduce performance gains from high-k to 10 percent or less compared with an oxynitride.

Hopes may also be too high that high-k will sharply reduce leakage current. Thompson estimates that 90 percent of current leakage occurs at the junctions of the source and drain--the so-called subthreshold leakage--with the remaining 10 percent occurring at the gate.

"I believe one or two companies, making processors for high-performance servers and desktops, will use high-k at the 45-nm generation. But they will get very little performance gain, compared with a high increase in wafer cost and complexity. The gains will be in the single digits--not that interesting for companies making wireless chip sets for cell phones," said Thompson, who spent 12 years at Intel's technology and manufacturing group in Hillsboro, Ore.