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EE Times: Semi News TI selects Applied for low-k at 45 nm |
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Mark LaPedus
(01/08/2007 11:57 PM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=196802091 |
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HALF MOON BAY, Calif. Texas Instruments Inc. is moving in a new direction for low-k dielectrics, selecting Applied Materials Inc.'s technology over films from rival Novellus Systems Inc. for the 45-nanometer node.
But TI (Dallas) is also struggling to ramp up its 193-nm immersion lithography scanners from ASML Holding NV at 45 nm. Chip giant TI is currently ramping up its 65-nm process, with plans to roll out its 45-nm technology in the near future. At the 65-nm node, TI has been using ASML's 193-nm ''dry'' scanners and Novellus' low-k films. At 45-nm, TI is switching gears and will use Applied's low-k film technology, dubbed Black Diamond, said Hans Stork, senior vice president and chief technology officer at TI, during a presentation at the Industry Strategy Symposium (ISS) here on Monday (Jan. 8). Applied's low-k technology is still being qualified at TI, Stork said. Black Diamond is a carbon-doped oxide film that uses Applied's chemical vapor deposition (CVD) tools. Meanwhile, at TI, ASML's 193-nm immersion lithography scanners are not meeting the necessary ''defect and throughput'' specifications at least for now, Stork said. ASML, he said, must tweak the alignment for its 1700i line of 193-nm immersion scanners at TI. The alignment issues are impacting the overall throughput for the immersion machines, he said. This is not surprising, given that the 1700i is a new class of tools. But by the time when TI goes into production at the 45-nn mode, Stork expects that ASML will resolve the problem. ''It's a new tool,'' he said. ''I'm not worried.'' Stork was also critical of low- and high-k dielectric films. Many leading-edge chip makers are struggling with low-k, which seems to be stuck at ''k effective'' levels of 2.9. ''There is a need for better low-k,'' Stork said. ''We haven't made very much progress.'' And not surprisingly, there are still major hurdles for the advent of high-k and metal gates for gate-stack applications, he said. TI is not expected to use high-k at the 45-nm node, he said. One saving grace for chip makers is strained engineering, which has proved to boost mobility in next-generation transistor designs. ''Strained engineering is the best thing since sliced bread,'' he said.
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