2. Alliances are linchpin of mega memory fabs
 

Mike Clendenin     /EETimes                                                                                               (05/14/2007 4:35 AM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=199501546

TAIPEI, Taiwan — In DRAM and NAND, the big are getting bigger, with a little help. A new report finds that the massive sums needed to build and operate state-of-the-art fabs will strengthen new and old alliances in the memory business.
DRAM and NAND flash are in the process of coalescing into just a few groups to share both development and fab costs, according to Strategic Marketing Associates. "We estimate the Toshiba-SanDisk joint venture, Flash Alliance, will spend as much as $10 billion to fully equip their newest fab," said George Burns, president of the market research firm.

The 300mm Fab 4, when fully ramped, will have a monthly capacity of more than 210,000 wafers. "If Fab 4 were a country, it would be ranked number eight in terms of capacity, just behind France, but ahead of Ireland."

The average capacity of a 300mm wafer DRAM or NAND flash fab had risen from 40,000 wafers in 2004 to 60,000 by the end of 2006 and will reach 80,000 wafers by 2009, according to SMA's recent quarterly report. The value of new fabs beginning production this year will be $31 billion — 58 percent of which will be DRAM and NAND. Next year, their share will be even higher, the researcher estimates.

The rising cost of building and outfitting these fabs will continue to push manufacturers into forging new alliances or expanding old ones. Other than Samsung Electronics and ProMOS Technologies, all major DRAM and NAND flash memory manufacturers have formed joint manufacturing ventures that involve technology licensing as well as development, Burns said.

"Most of these alliances are fairly new," Burns said, "except for Toshiba-SanDisk and that led by Qimonda. The IM Flash alliance joint venture with Intel and Micron was formed at the end of 2005, Rexchip (Elpida and Powerchip) was formed last year and the Hynix/SanDisk alliance this year. But, regardless of their age, these alliances are becoming more and more essential."

As a group, these companies will more than double their DRAM and NAND flash capacity by the end of 2010, according to the report. "The total cost of these DRAM and NAND fabs will exceed $100 billion," Burns said. "This growth would not be possible without these alliances."
 

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3. Costs cast ICs into Darwinian struggle

Mark LaPedus                                                                                                 (03/30/2007 4:00 PM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=198701495


San Jose, Calif. — The IC business is fast becoming unaffordable for all but the wealthiest chip makers.

Rising fab and chip-design costs are creating a new elitism, with the well-heeled few able to shoulder the burden and the mass of suppliers squeezed out, according to data from one design tool vendor. The trend will become even more pronounced starting at 45-nanometer manufacturing, Synopsys Inc. predicted at last week's International Symposium on Quality Electronic Design (ISQED) here.

In the new IC world order, fewer integrated device manufacturers (IDMs) can afford to build fabs, while

only an elite group may be able to develop leading-edge IC designs over time. At the 45-nm node, a new 300-mm fab costs about $3 billion, process technology R&D runs $2.4 billion and a "mask set" is up to $9 million, Synopsys said. Test costs, meanwhile, continue to be flat.

IC design costs range between $20 million and $50 million, the EDA company estimated. And there's a new problem on the block: process variation. Identified as one of the new "pressure points" at the 45-nm node, variation is becoming one of the root causes of chip failures.

Much of the data is uncertain for the 32-nm node and beyond, but some say that by then, a new 300-mm fab could go for $10 billion, as process R&D costs reach $3 billion and design costs $75 million.

"I am not saying that the semiconductor industry has reached a stalemate," said Tom Williams, a fellow at Synopsys (Mountain View, Calif.). "But making the jump to the 65- and 45-nm nodes will involve a very small part of the [chip-making] population. You will see people jumping at the 45- and 32-nm nodes too, but only the elite few will be able to afford it."

There are two sides of the economic problem in the semiconductor industry: IC design and manufacturing. Both IDMs and fabless design houses are affected.

On the manufacturing side, Williams painted a troubling set of trends. Overall plant costs could escalate faster than expected, he said, due in part to the soaring prices for semiconductor manufacturing equipment, materials and a forgotten line item: R&D.

For R&D expenses alone, an IDM must spend an estimated $1.5 billion just to develop a 65-nm process technology, but that figure is expected to jump to $2.4 billion for the 45-nm node and $3 billion for the 32-nm era, Williams said. Those totals include the CAD tools, process models and related costs, but not the fab or equipment.

But few, if any, IDMs will be able to achieve a real return on investment (ROI) for R&D. For example, Williams said, to achieve an ROI at the 65-nm node, an IDM must generate a total of $8.3 billion in sales per year. In 2006, only five IDMs had sales of $8.3 billion or more: Intel, Samsung, Texas Instruments, STMicroelectronics and Toshiba, according to IC Insights Inc. (Scottsdale, Ariz.).

The ante gets upped in subsequent process generations. An IDM must generate $13.3 billion and $16.7 billion in annual sales to achieve an ROI at the 45- and 32-nm nodes, respectively, said Williams. Based on last year's sales, only Intel Corp. and Samsung Electronics Co. Ltd. could sustain a real ROI in overall R&D costs.

To recoup these types of investments, chip makers will be under more pressure to develop products at higher volumes, Williams said. Many of those chips will be targeted for the high-volume consumer apps, added David Lammers, an analyst with VLSI Research Inc. (Santa Clara, Calif.) and editor of a professional site called WeSRCH.com.

Real men have fab consortiums

Lammers also agreed that fab costs are skyrocketing. For example, a new 300-mm "gigafab," which is capable of making 100,000 wafers a month, could cost between $5 billion and $10 billion in the near term, Lammers said.

Mask costs, on the other hand, "have not gone up, as some people have feared [they would]," he said. "They can't. People can't afford it."

In Lammers' view, the R&D picture is also less bleak than Williams of Synopsys paints it. "Intel is about the only logic company that can do it alone," Lammers said, but many IDMs have spread their R&D and fab costs by "following the consortium model."

One example is IBM Corp.'s manufacturing-technology alliance, which includes AMD, Chartered, Freescale, Infineon, Samsung, Sony and Toshiba. In this "fab club," the vendors plan to share the R&D costs at the 65-nm node and beyond.

Most IDMs have also embraced foundries to one degree or another, in an effort to reduce their manufacturing costs. In fact, over the years, a growing number of IDMs have adopted a "fab lite" or "process lite" strategy, due in part to soaring fab and R&D costs.

One of the more and recent dramatic examples is Texas Instruments Inc. (Dallas). TI stunned the industry in January when it announced it would drop the costly business of digital-logic process development and rely on foundry partners for those technologies. TI has decided to halt internal development at the 45-nm node and use foundry-supplied processes at 32 nm and beyond, although it will continue to invest in analog fabs. The intent is to cut costs and free up resources to focus on design.

Design woes

On anther front, IC design costs continue to soar. According to Synopsys' figures, they are projected to jump from $20 million to $50 million on average for the 45-nm node, to somewhere around $75 million for the 32-nm era.

At the same time, IC design complexity "has been rising exponentially," said Sanjiv Taneja, vice president and general manager for Cadence Design Systems Inc., in a keynote at the ISQED event. So future designs must address new problems, such as power, new physical effects in lithography, process variation and product-specific yield learning, he said.

A set of more general but troubling IC-design issues also surfaced at ISQED, including quality and reliability. "Today, we are still struggling to ensure quality in design," Chi-Foon Chan, president and COO of Synopsys, said here.

And then there is a new problem the industry is stubbing its toe on: process variation. Difficulties arise because the values on an IC can vary and are uncontrollable by the designer. Device properties can vary due to doping gradients and other process steps.

Still to be seen, however, is how chip makers will tackle process variation issues. Variation "has become a serious problem in sub-100-nm designs, and is most pronounced in SRAM designs," according to an ISQED paper from IBM.

Statistical timing analysis addresses a piece of the problem, but IBM took another approach to variation. In its paper, the company said it has devised gate-leakage monitor circuitry in a dense array of addressable devices, derived from an SRAM-based silicon-on-insulator cell. This circuitry monitors the gate leakage on an SRAM cell at 65 nm.

Also at ISQED, the Tokyo Institute of Technology (Yokohama, Japan) took a somewhat similar approach. It has developed a MOS transistor-array structure for use in the measurement of subthreshold leakage variation.

The Massachusetts Institute of Technology took a different tack by tipping a three-layer attack on variation in ICs: design-for-manufacturability (DFM), statistical metrology and advanced process control (APC).

"The key idea in statistical metrology is that variation must be measured and modeled," said professor Duane Boning, associate head of the department of electrical engineering and computer science at MIT. "With an understanding of variation enabled by statistical metrology, one can attack that variation in two different directions—one downward within the fabrication process, and one upward within circuit and system design."

APC, for its part, tries to "reduce process variation through sensing and control during fabrication," he said. "Design- for-manufacturability seeks methods to improve performance and yield."

Boning also urged the industry to research and invest in this arcane but critical technology niche. "Tools and techniques are needed in all these areas," he said. "Improvements in and increased linkage between statistical metrology and DFM will be particularly important."

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