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Is Resistive RAM (RRAM) The Future Flash Memory?



Below is an overview of Resistive RAM (RRAM) by Bogdan Govoreanu, from IMEC . This new flash memory technolgy is worth watching.


Eli Harrari, Sandisk founder, CEO, and Chairman from its founding until January 2011 in his ISSCC Plenary talk stated that 3D-RRAM " has a real shot at becoming the next big game-changer in the second half of this decade".

Eli Harrari foresaw upcoming changes in non volatile memory. He converted Sandisk from supporting both NOR and NAND flash to only NAND long before other companies saw the upcoming accelerating growth in NAND.

Ron Maltiel




Resistive RAM for next-generation nonvolatile memory
Bogdan Govoreanu, imec Leuven                                               3/12/2012 1:25 PM EDT


Since its introduction in 1988 by Toshiba1, NAND flash nonvolatile memory has undergone an unprecedented growth, becoming one of today’s technology drivers. Although NAND flash memory has scaled to 1x-nm feature sizes, shrinking cell sizes reduce the number of electrons stored on the floating gate. Resistive RAM (RRAM) provides an alternative. In this article, we review the main performance figures of hafnium-oxide (HfO2)-based RRAM cells4 from a scalability perspective, outlining their strengths as well as the main challenges ahead.

A NAND flash nonvolatile memory cell, usually a floating gate transistor, implements the memory function by charge stored on the floating gate. With a charge transfer mechanism onto/from the storage medium that relies on tunneling and a serial (string) architecture, NAND memory features high operating voltages (with associated chip area consumption for the on-chip voltage generation), rather long cell program/erase (P/E) times, and slow read-access times. These drawbacks are, however, compensated for by the very compact array architecture and extremely low energy-consumption-per-bit operation, which eventually enabled fabrication of high-density memory arrays, at low cost and with a chip storage capacity increasing impressively.
During its extraordinary evolution, NAND flash has often met seemingly insurmountable barriers. Technological, architectural, and design innovations complemented each other, however, enabling continued scaling. Nowadays, NAND flash memory seems to have found the way toward the realm of 1x-nm feature size, with major players fighting for each nanometer of cell shrinkage, not to mention for supremacy. Nevertheless, the scaling of cell size leads to gradual reduction of the number of electrons stored on the floating gate, with a projected number of less than 30 electrons for memorizing a (multilevel) cell state, for an assumed 15-nm feature size2.

Resistive RAM (RRAM), just like phase-change memory (PCM), is emerging as a disruptive memory technology, implementing memory function in a resistance (rather than stored charge), the value of which can be changed by switching between a low and a high level. Although the phenomenon of reversible resistance switching has been since the 1960s, recent extensive research in the field has led to the proposition of several concepts and mechanisms through which this reversible change of the resistance state is possible. The distinctive feature of most RRAM concepts3 consists of the localized, filamentary nature of a conductive path formed in an insulating material separating two electrodes (a metal-insulator-metal (MIM) structure), corresponding to the on-, low-resistance state. This attribute was immediately associated with a high scalability potential, beyond the limits currently predicted for flash memory.

Resistive memory structures

Even if many materials reported to date exhibit good resistive switching properties, the success of a future RRAM technology is critically dependent on the ability to integrate these materials/switching structures into a conventional, supporting baseline technology, with cost as a key success factor. Not surprisingly, fab-friendly and accessible materials such as HfO2, zirconium dioxide, titanium dioxide, tantalum dioxide/ditantalum pentoxide, etc, which showed resistive switching behavior, have received the highest attention.

A thin HfO2 dielectric film sandwiched between two metal electrodes was shown to have resistive switching properties, either uni- or bipolar, depending on the materials used as electrodes and on the method to deposit the active (oxide) film. The bipolar operation of HfO2, requiring voltages of opposite polarity to switch on/off the cell, is believed to be due to the formation of conductive paths (filaments) associated with presence of oxygen vacancies (VO), which can be ruptured/restored through oxygen/VO migration under electric field and/or locally enhanced diffusion. The bipolar operation of HfO2 is preferred for its increased immunity to disturbs and over reset. The formation of the filament (forming, or electroforming) is believed to take place along pre-existing weak spots in the oxide, for instance along the grain boundaries in case of a polycrystalline HfO2, which presumably have larger amount of defects and also a higher oxygen diffusivity compared to the bulk of the material.5,6

An alternative approach is to use a metal/oxide material system7 with a reactive (capping) metal, capable of chemically reducing the HfO2. Although a Hf/HfO2 system may seem an obvious choice, selection of hafnium as a cap layer is supported by thermodynamic considerations that indicate a low oxide formation energy, when reducing HfO2. A similar property is found for the titanium/HfO2 case. In the Hf/HfO2 system, hafnium acts as an oxygen buffer layer that allows, under electrical stimuli, the production of oxygen-deficient off-stoichiometric oxide, thus favoring formation of the switching filament. Furthermore, conventional physical vapor deposition (PVD) titanium nitride was used to define the bottom and top electrodes (BE/TE) in a crossbar-patterned configuration.

To achieve best flexibility and controllability of RRAM device operation, the resistive memory structure was connected serially with an nMOS transistor, which acts as a cell selector. Figure 1a shows a top view scanning-electron-microscopy (SEM) picture of a test structure, while high-resolution transmission-electron-microscopy (TEM) cross-sections of the structure along the main directions, visualizing the BE/TE are shown in figure 1b and figure 1c. The smallest fully functional working structures processed4, feature an effective area of around 10 x 10 nm2, defined by the BE width and by the width of the TE/Hf-cap tip resulting after the crossbar patterning.



Figure 1: Top SEM-view of a crossbar resistive element (a) and high-resolution TEM cross-sections of the bottom- (b) and top-electrode (c).



The oxide thickness is the main parameter determining the value of the forming voltage (VF), which is typically the highest voltage and needed only once, to get the RRAM cells ready for operation. In contrast, the Set (on-switching) and Reset (off-switching) voltages are lower and, in a common situation, do not depend on oxide thickness. This difference makes it possible that VF can be then reduced by thinning the oxide layer, without interfering with normal cell operation. Furthermore, aggressive oxide thinning may eventually lead to forming-free operation.

The Set/Reset (S/R) voltages, as well as the levels of the on/off states, turn out to be essentially independent not only of oxide thickness, but also of cell size. Although operating the cell in extreme conditions (i.e. with very deep Reset or strong Set switching) may turn these characteristics invalid, the common situation is consistent with the filamentary nature of the conductive path; furthermore, it supports the model of a partial rupture and restoration of the filament during device operation. Eventually, the oxide thickness corresponding to forming-free operation, confirmed experimentally to be in the range of 2 to 2.5 nm, is indicative of the extent of the ruptured portion of the conductive filament.



Electrical performance and reliability

Given the structure asymmetry induced by the presence of the hafnium layer, the RRAM cells are best operated in bipolar mode with positive polarity on TE for the Set and forming operations and with negative polarity on TE for the Reset operation. In this section, we will discuss the most important performance and reliability figures of the HfO2-based RRAM cells.



Switching speed

To measure switching speed, we used a pulsed operation mode, exemplified here for a Reset switching. Thus, stimuli were applied on the sourceline (SL) and wordline (WL) of the serial 1T1R (1-transistor, 1-resistor) test vehicle, while the response was monitored with a digital oscilloscope on a small series resistance attached to the cell bitline (BL; see figure 2a) . The switching was time-confined to a maximum duration given by the width of the SL pulse, i.e. 10 ns. We carefully designed the experimental setup to minimize the impact of the parasitic elements (e.g. capacitances), having a reasonably short system time constant. The resistive element, initially in the on-state, switches to the off-state quickly, leading to a decrease of the signal within just 3 to 4 ns (see figure 2b). When taking into account the impact of the testing environment on the collected waveform, the observed transition time duration gives a higher margin for the intrinsic switching time, which can be shorter.



Figure 2: Schematics of the device under test (DUT), with applied stimuli and collected response (a) and waveforms corresponding to a Reset switching (b), sampled with a LeCroy WavePro 740Zi 4GHz oscilloscope. The 10-ns SL pulse (blue color), which enables switching, in contained in the longer WL pulse (red color) used to open up the transistor’s channel. The Reset switching is confirmed by the read-out (RO) of the cell current, which changes from high value (on-state) before the SL applied pulse to low value (off-state) after the pulse.





On/off window & operating voltages

The on/off window easily exceeds a factor of 10, with modest (<1 V) voltages applied for both S/R operations. Using higher amplitude pulses and switching verification will improve the on/off window by at least two orders of magnitude, as well as enhancing the uniformity of the switching operations (see figure 3a), which may open up paths for multilevel operation.


Figure 3: Typical on/off window (expressed in read-out cell current) achievable with sub-3-V pulsed operation, with verify (a) and Reset pulse amplitude-duration voltage-time trade-off, showing no significant degradation when scaling cell size from 1 um2 down to 10 x 10 nm2 (b). Data are for an oxide film thickness of 10 nm. The dashed lines are guide for the eye. Similar conclusions hold for Set switching (not shown).



The voltage-time dilemma is a popular term used to express the limited ability of RRAM to display nonlinearity. This is however not specific to RRAM, but present in virtually all memory structures, which ideally need to on one hand allow for indefinitely long stability under no or low-electrical stimuli (for retention, read-out and disturbs immunity), while on the other hand providing fast change of state under operating stimuli (for P/E or S/R).

The S/R voltages required to operate these cells thus display the usual trade-off with time. Nevertheless, the pulse amplitude-time dependence shows that the cells can still be operated with voltages well below 3 V, even for pulses as short as 10 ns. Furthermore, in a comparison of large area cells (in the order of 1 um2) with smallest-size cells (of 10 x 10 nm2), the voltage-time characteristics maintain similarity (see figure 3b), which shows that we should expect no considerable performance degradation when considering aggressively scaled structures. Compared to NAND flash, RRAM has the benefits of low-operating voltages.



Reliability: retention & endurance

The usual 10 year requirement for NVM retention is met by most of the RRAM cells, with a median cell reaching this limit at an extrapolated temperature of around 100°C. As expected, retention turns out to be most critical for the on-state, where retention loss is attributed to filament dissolution. Retention improvement is possible through material optimization and careful sealing of the active region with oxygen-free layers.

Endurance tests performed on unoptimized samples showed cycling of at least 10 Mcycles in a single shot. The failure at the end of the tests was, however, recoverable with a stronger stimulus to “unlock” them from the stuck state, and cycled again with adjusted slightly stronger conditions. These facts suggest that careful balancing of the S/R test conditions, next to process improvement, may allow superior reliability and extended device lifetime, which can well exceed billion cycles, even on the smallest device sizes. This figure is far above the conventional requirement for flash memory, pinpointed to 100 kcycles, although reference value for data storage flash is commonly lowered down 10 kcycles, on arguments of practical, as well as economical nature associated with a commodity product.

Scalability, energy consumption, and cell array considerations

The data discussed so far provide evidence of RRAM operation on an effective area of nearly 10-x-10-nm2 without compromising any of the major performance or reliability figures. This size is the smallest reported to date, for HfO2-based RRAM cells and demonstrate cell scalability in the nanometer range, which is beyond scaling limits of NAND flash. Filament formation has been observed experimentally, for instance on TEM pictures, for metallic filaments, such as those formed in nitrous oxide RRAM.


Figure 4: Extracted filament size for 10-x-10-nm2 cells, operated with 10-ns pulse duration. The filament was asssumed cylindrical, with a saturated sub-stochiometric hafnia resistivity.8


In the cells under discussion here, conductive paths presumably formed by oxygen vacancies corresponding to locally lower fractions of oxygen content in the active oxide layer are hard to detect, due to resolution limits of the physical characterization methods. Oxygen-deficient HfO2, however, has a resistivity that correlates with the amount of oxygen-deficiency, but eventually saturates for highly deficient stable sub-oxides, at a value still significantly higher than that of metallic Hf.8 When combined with experimental electrical data corresponding to on-state (measured on the smallest 10 x 10 nm2 HfO2-based RRAM cells), this property allowed extracting the radius of an assumed-cylindrical filament, with a median value of nearly 1 nm. Although an estimate, this result suggests intrinsic scalability of the resistive memory element in the few-nanometer range.

One of the key features of NAND flash technology is the extremely low power required to write/erase a single cell, as it only involves very low (Fowler-Nordheim) tunneling currents. This translates, in spite of the need to use high P/E voltages, into a low energy used to operate a cell, even with the long specific cell P/E times, thus enabling a high throughput in NAND flash. RRAM, by contrast, works at much lower voltages and on/off switching is several orders of magnitude faster than for NAND cells. The current is, however, significantly larger and even if RRAM scores well in comparison with MRAM9 and PCM technologies10,11 there are concerns about the circuit level implications.


Figure 5: Benchmarking of HfO2-based RRAM in relation with existing (NAND flash) and other emerging technologies (MRAM, PCM). An improvement direction implying use of shorter pulses is identified experimentally.4

When we consider the switching energy per bit operation, RRAM is approaching the performance of NAND flash, given the actual peak current levels during switching as high as a few tens of microamps. Crossing below a 10-fJ-NAND flash border would require nanosecond switching speeds, or sub-microamp switching currents; paths to meeting these requirements are currently pursued.

RRAM has device-level characteristics that meet most of the nonvolatile memory requirements. It furthermore shows scalability potential in an area that is thought to be inaccessible to NAND flash. To be able to exploit these strengths at circuit/system level, RRAM must overcome cell read-out interference12 that may cause in erroneous read out of the (HRS) cell state, due to so-called sneak-current paths. Alleviation of this issue requires a bidirectional selector device. The control transistor in a 1T1R structure provides this functionality and it is, in fact, a potential solution for memory arrays in which density is not the main concern. For data storage applications, however, achieving highest memory density should aim at a cell footprint of around 4F2 (with F being the feature size), implementation of which will, most likely, require the use of a two-terminal selector device13 or a rectification function built into the memory element itself (self-rectifying resistive memory). Research achievements in this direction, complemented by consideration of practical possibilities to increase effective density by using 3D architectures14 for meeting cost effectiveness, will eventually determine the success of RRAM as the future nonvolatile memory of choice.

In summary, HfO2-based RRAM shows great promise for future generation nonvolatile memory, offering a fab-friendly option, with performance characteristics that qualify it for a fast, low-voltage, low-energy-consumption memory, with a good and perfectible reliability, as demonstrated for fully-functional 10-nm-size devices and with inferred intrinsic scalability down to a few-nanometer size. Further improvement in reliability and additional “in-the-footprint” or built-in selection functionality set important milestones ahead on the road to becoming tomorrow’s nonvolatile memory.



Note: This article is based on the work reported at IEDM 2011 by the Emerging Memory Devices Program team of imec Leuven.4



References

1. M. Momodomi et al, IEDM Tech. Dig, pp. 412-415, 1988.

2. K. Prall, Proc. NVSMW, pp. 5-10, 2007.

3. R. Waser, IEDM Tech. Dig, pp. 289-292, 2008.

4. B. Govoreanu et al, IEDM Tech. Dig, pp. 729-732, 2011.

5. G. Bersuker et al, IEDM Tech. Dig, pp. 456-459, 2010.

6. U. Brossmann et al, J.Appl.Phys, 85(11): 7646-7654, 1999.

7. B. Govoreanu et al, Ext. Abstr. SSDM, pp. 1005-1006, 2011.

8. E. Hildebrandt et al, Appl.Phys.Lett, 99: 112902, 2011.

9. K. Tsukida et al, ISSCC Dig, pp. 258-259, 2010.

10. R. Annunziata et al, IEDM Tech. Dig, pp. 97-100, 2010.

11. S.H. Lee et al, IEDM Tech. Dig, pp. 47-50, 2011.

12. M-J. Lee et al, IEDM Tech. Dig, pp. 771-774, 2007.

13. K. Gopalakhrishnan, VLSI Tech. Symp, pp. 205-206.

14. I.-G. Baek, IEDM Tech. Dig, pp. 737-740, 2011.



About the author

Bogdan Govoreanu is currently appointed as a principal scientist with imec Leuven and a staff member of the Memory Device Design Group, Process Technology Unit, carrying out research in the field of emerging memory devices with focus on resistive switching memory. He received his Ph.D.in Applied Sciences in 2004 from the University of Leuven (Katholieke Universiteit Leuven). During his career, Govoreanu has authored or co-authored over 80 research papers and holds/has filed six US and European patents/patent applications. He is also an IEEE Senior Member

 

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