The winner for the next flash memory approach is still not clear. A strong candidate is stacking memory NAND dies one on top of another. The dies are connected using Through Silicon Vias (TSV). Toshiba has a different approach to 3D " not stacking NAND chips one atop the other but rather stacking layers of NAND in a single chip" See more details below.
The key concern for next NAND generations is the 5 years lead time to build a new $5 billion fab, which could be designed for the wrong process technology.
It does not help that "the number of electrons in a gate decreases as the process geometry size is reduced....below 10nm the number of critical electrons in a gate can be as few as 10 – and that losing 10 electrons could seriously affect the gate's functioning. He says there are a variety of issues with such very small cells, such as bit-line loading, interference and leakage, leading to signal retention and reliability issues, for which, currently, there are no solutions.
copyright 2012 Ron Maltiel all rights reserved