Process Challenges of 3D (Vertical Transistors)

​The article linked in this blog describes the drive toward 3D vertical transistors above the surface of the chip's die. 3D NAND represents a major departure from today’s planar NAND. 

.In 2D NAND, the fabrication process is dependent on advanced lithography. In 3D NAND, though, vendors are using trailing-edge 40 nm to 20 nm design rules. Lithography is still used, but it isn’t the most critical step. So for 3D NAND, the challenges shift from lithography to deposition and etch.

However, the new 3D processes are not easy to implement.

3D NAND introduces a number of new and difficult process steps to the semiconductor industry…it has introduced several fairly complex and new processes. Uniformity of these processes is critical. So, from my perspective, the challenges here are focused on variability control of several key processes.

It will be interesting how well Intel and Micron XPoint (see SSD, 3D Vertical NAND, or 3D XPoint?) products will succeed against current 3D products (see November 2012 3D NAND flash is coming).

​Read more in the semiengineering.com article: How to Make 3D NAND.